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    Searched refs:Disp (Results 1 - 25 of 54) sorted by relevancy

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  /src/external/gpl3/binutils/dist/include/opcode/
tic30.h 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
    [all...]
  /src/external/gpl3/binutils.old/dist/include/opcode/
tic30.h 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
    [all...]
  /src/external/gpl3/gdb.old/dist/include/opcode/
tic30.h 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
    [all...]
  /src/external/gpl3/gdb/dist/include/opcode/
tic30.h 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/
SystemZMCCodeEmitter.cpp 187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
188 assert(isUInt<4>(Base) && isUInt<12>(Disp));
189 return (Base << 12) | Disp;
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
198 assert(isUInt<4>(Base) && isInt<20>(Disp));
199 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
209 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
210 return (Index << 16) | (Base << 12) | Disp;
    [all...]
SystemZInstPrinter.cpp 27 int64_t Disp, unsigned Index,
29 O << Disp;
211 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
213 O << Disp << '(' << Length;
224 uint64_t Disp = MI->getOperand(OpNum + 1).getImm();
226 O << Disp << "(";
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/MCTargetDesc/
MSP430InstPrinter.cpp 71 const MCOperand &Disp = MI->getOperand(OpNo+1);
84 if (Disp.isExpr())
85 Disp.getExpr()->print(O, &MAI);
87 assert(Disp.isImm() && "Expected immediate in displacement field");
88 O << Disp.getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelDAGToDAG.cpp 63 int64_t Disp;
83 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(),
152 dbgs() << "\nDisp: " << Disp;
228 // If Address Mode represents Frame Index store FI in Disp and
232 SDValue &Disp, SDValue &Base) {
234 Disp = getI32Imm(AM.Disp, DL);
247 Sym = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(), MVT::i32, AM.Disp,
254 AM.Disp, AM.SymbolFlags);
259 assert(!AM.Disp && "Non-zero displacement is ignored with ES.")
    [all...]
M68kRegisterInfo.cpp 172 // NOTE Base contains the FI and we need to backtrace a bit to get Disp
173 MachineOperand &Disp = MI.getOperand(FIOperandNum - 1);
176 int Imm = (int)(Disp.getImm());
209 Disp.ChangeToImmediate(FIOffset + Imm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/
PPCDisassembler.cpp 232 uint64_t Disp = Imm & 0xFFFF;
256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
267 uint64_t Disp = Imm & 0x3FFF;
277 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
290 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
294 Inst.addOperand(MCOperand::createImm(Disp));
305 uint64_t Disp = Imm & 0xFFF;
309 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
320 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
324 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelDAGToDAG.cpp 47 int16_t Disp = 0;
70 errs() << " Disp " << Disp << '\n';
119 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
145 AM.Disp += G->getOffset();
150 AM.Disp += CP->getOffset();
187 AM.Disp += Val;
230 AM.Disp += Offset;
245 SDValue &Base, SDValue &Disp) {
262 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N)
    [all...]
MSP430AsmPrinter.cpp 110 const MachineOperand &Disp = MI->getOperand(OpNum+1);
115 if (Disp.isImm() && Base.getReg() == MSP430::SR)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86OptimizeLEAs.cpp 85 const MachineOperand *Disp)
86 : Disp(Disp) {
103 return isSimilarDispOp(*Disp, *Other.Disp);
110 const MachineOperand *Disp;
136 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
137 assert(Val.Disp != PtrInfo::getTombstoneKey() &&
147 switch (Val.Disp->getType()) {
152 Hash = hash_combine(Hash, Val.Disp->getIndex())
    [all...]
X86InstrBuilder.h 40 /// with BP or SP and Disp being offsetted accordingly. The displacement may
55 int Disp;
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
83 MO.push_back(MachineOperand::CreateImm(Disp));
114 AM.Disp = Op3.getImm();
185 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
187 MIB.addImm(AM.Disp);
X86ISelDAGToDAG.cpp 70 int32_t Disp;
83 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
129 dbgs() << " Disp " << Disp << '\n'
221 SDValue &Scale, SDValue &Index, SDValue &Disp,
225 SDValue &Index, SDValue &Disp, SDValue &Segment);
228 SDValue &Scale, SDValue &Index, SDValue &Disp,
231 SDValue &Scale, SDValue &Index, SDValue &Disp,
234 SDValue &Scale, SDValue &Index, SDValue &Disp,
240 SDValue &Index, SDValue &Disp,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelDAGToDAG.cpp 58 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
60 int64_t Disp;
65 : Form(form), DR(dr), Base(), Disp(0), Index(),
91 errs() << " Disp " << Disp;
159 SDValue &Base, SDValue &Disp) const;
161 SDValue &Base, SDValue &Disp, SDValue &Index) const;
165 // Base and Disp respectively.
167 SDValue &Base, SDValue &Disp) const;
171 // base and displacement in Base and Disp respectively
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
SystemZDisassembler.cpp 294 uint64_t Disp = Field & 0xfff;
297 Inst.addOperand(MCOperand::createImm(Disp));
304 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
315 uint64_t Disp = Field & 0xfff;
318 Inst.addOperand(MCOperand::createImm(Disp));
327 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
330 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
339 uint64_t Disp = Field & 0xfff;
342 Inst.addOperand(MCOperand::createImm(Disp));
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/
unload.exp 66 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
79 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
102 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
120 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/
unload.exp 67 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
80 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
103 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
121 "Num Type\[ \]+Disp Enb Address\[ \]+What\r?
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelDAGToDAG.cpp 38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
65 SDValue &Disp) {
73 Disp = CurDAG->getTargetConstant(0, dl, MVT::i8);
100 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16);
112 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8);
225 SDValue Base, Disp;
227 if (SelectAddr(Op.getNode(), Op, Base, Disp)) {
229 OutOps.push_back(Disp);
260 SDValue Base, Disp;
279 Disp = CurDAG->getTargetConstant(ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8)
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
MachineInstrBuilder.h 284 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
291 TargetFlags = Disp.getTargetFlags();
293 switch (Disp.getType()) {
297 return addImm(Disp.getImm() + off);
299 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
302 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
305 return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 68 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
385 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp);
404 if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Disp.getExpr())))
452 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
456 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), StartByte, OS,
500 if (Disp.isImm() && isInt<8>(Disp.getImm())) {
501 if (Disp.getImm() == 0 && RMfield != 6) {
508 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, StartByte, OS, Fixups)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
SystemZAsmParser.cpp 110 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
119 const MCExpr *Disp;
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
192 Op->Mem.Disp = Disp;
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
307 addExpr(Inst, Mem.Disp);
313 addExpr(Inst, Mem.Disp);
320 addExpr(Inst, Mem.Disp);
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
FileSystem.h 954 /// @param Disp Value specifying the existing-file behavior.
962 CreationDisposition Disp, FileAccess Access,
972 /// @param Disp Value specifying the existing-file behavior.
979 Expected<file_t> openNativeFile(const Twine &Name, CreationDisposition Disp,
1043 CreationDisposition Disp = CD_CreateAlways,
1045 return openFile(Name, ResultFD, Disp, FA_Write, Flags, Mode);
1062 CreationDisposition Disp,
1065 return openNativeFile(Name, Disp, FA_Write, Flags, Mode);
1084 CreationDisposition Disp,
1087 return openFile(Name, ResultFD, Disp, FA_Write | FA_Read, Flags, Mode)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
X86Operand.h 59 const MCExpr *Disp;
141 if (Mem.Disp)
142 PrintImmValue(Mem.Disp, ",Disp=");
176 return Mem.Disp;
664 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
669 Res->Mem.Disp = Disp;
685 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
701 Res->Mem.Disp = Disp
    [all...]

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