HomeSort by: relevance | last modified time | path
    Searched refs:DppCtrl (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 819 } else if (Imm <= DppCtrl::QUAD_PERM_LAST) {
825 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
826 (Imm <= DppCtrl::ROW_SHL_LAST)) {
829 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
830 (Imm <= DppCtrl::ROW_SHR_LAST)) {
833 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
834 (Imm <= DppCtrl::ROW_ROR_LAST)) {
837 } else if (Imm == DppCtrl::WAVE_SHL1) {
843 } else if (Imm == DppCtrl::WAVE_ROL1) {
849 } else if (Imm == DppCtrl::WAVE_SHR1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNDPPCombine.cpp 403 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl);
404 assert(DppCtrl && DppCtrl->isImm());
405 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) {
SIInstrInfo.cpp 4258 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
4259 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
4260 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) ||
4261 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) ||
4262 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) |
    [all...]
SIDefines.h 675 enum DppCtrl : unsigned {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 1000 case ImmTyDppCtrl: OS << "DppCtrl"; break;
3953 unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
3955 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {
7654 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) ||
7655 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) ||
7656 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) ||
7657 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) |
    [all...]

Completed in 28 milliseconds