| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.h | 57 const TargetRegisterClass *DstRC,
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| AVRRegisterInfo.cpp | 282 const TargetRegisterClass *DstRC,
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS);
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| InstructionSelect.cpp | 176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
177 if (DstRC)
178 MRI.setRegClass(SrcReg, DstRC);
226 auto DstRC = MRI.getRegClass(DstReg);
227 if (SrcRC == DstRC) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 154 const TargetRegisterClass *DstRC = DstReg.isVirtual()
158 return std::make_pair(SrcRC, DstRC);
162 const TargetRegisterClass *DstRC,
164 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
169 const TargetRegisterClass *DstRC,
171 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
172 TRI.hasVectorRegisters(DstRC);
237 const TargetRegisterClass *SrcRC, *DstRC;
238 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
240 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)
[all...] |
| AMDGPUInstructionSelector.cpp | 104 const TargetRegisterClass *DstRC
108 if (!DstRC || DstRC != SrcRC)
111 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) &&
477 const TargetRegisterClass *DstRC =
479 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
516 const TargetRegisterClass *DstRC =
518 if (!DstRC)
521 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8)
[all...] |
| SIRegisterInfo.h | 247 const TargetRegisterClass *DstRC,
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| SIInstrInfo.cpp | 1196 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
1198 if (RI.hasAGPRs(DstRC))
1200 if (RI.getRegSizeInBits(*DstRC) == 32) {
1201 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1202 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1204 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
2545 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2546 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
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| HexagonRegisterInfo.cpp | 349 const TargetRegisterClass *DstRC, unsigned DstSubReg,
360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
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| HexagonGenInsert.cpp | 686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
690 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
693 if (DstRC != SrcRC)
695 if (DstRC == InsRC)
698 if (DstRC == &Hexagon::DoubleRegsRegClass)
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 151 const TargetRegisterClass *DstRC,
156 if (DstRC == SrcRC)
181 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
184 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
186 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
187 return !TRI.getCommonSubClass(SrcRC, DstRC);
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
436 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
485 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO)
[all...] |
| PeepholeOptimizer.cpp | 477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
479 if (!DstRC)
585 MRI->constrainRegClass(DstReg, DstRC);
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| RegisterCoalescer.cpp | 479 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
487 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
494 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
498 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
501 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
516 CrossClass = NewRC != DstRC || NewRC != SrcRC;
1351 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1353 TRI->getCommonSubClass(DefRC, DstRC);
1882 auto DstRC = MRI->getRegClass(CP.getDstReg());
1887 std::swap(SrcRC, DstRC);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstructionSelector.cpp | 110 const TargetRegisterClass *DstRC,
250 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
252 if (SrcRC != DstRC) {
254 Register ExtSrc = MRI.createVirtualRegister(DstRC);
278 const TargetRegisterClass *DstRC =
288 if (DstRC != SrcRC) {
289 I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
298 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) {
299 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
682 // Returns true if DstRC lives on a floating register class an
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass;
127 Register NewVReg = MRI.createVirtualRegister(DstRC);
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| PPCVSXSwapRemoval.cpp | 922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
923 Register NewVReg = MRI->createVirtualRegister(DstRC);
936 if (DstRC == &PPC::VRRCRegClass) {
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| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 204 const CodeGenRegisterClass *DstRC = nullptr;
282 if (DstRC) {
283 if (DstRC != RC && !DstRC->hasSubClass(RC))
286 DstRC = RC;
485 const CodeGenRegisterClass *DstRC = nullptr;
493 DstRC = &Target.getRegisterClass(Op0Rec);
494 if (!DstRC)
533 DstRC))
583 DstRC,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 156 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
160 const TargetRegisterClass *DstRC,
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| SystemZRegisterInfo.cpp | 379 const TargetRegisterClass *DstRC,
387 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.h | 132 /// SrcRC and DstRC will be morphed into NewRC if this returns true
134 unsigned SubReg, const TargetRegisterClass *DstRC,
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| AArch64RegisterInfo.cpp | 780 /// SrcRC and DstRC will be morphed into NewRC if this returns true
783 const TargetRegisterClass *DstRC, unsigned DstSubReg,
786 ((DstRC->getID() == AArch64::GPR64RegClassID) ||
787 (DstRC->getID() == AArch64::GPR64commonRegClassID)) &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 139 const TargetRegisterClass *DstRC,
865 const TargetRegisterClass *DstRC;
866 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI);
868 if (!DstRC) {
908 unsigned DstSize = TRI.getRegSizeInBits(*DstRC);
916 getSubRegForClass(DstRC, TRI, SubReg);
920 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg);
927 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg);
956 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
2829 const TargetRegisterClass *DstRC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 204 /// SrcRC and DstRC will be morphed into NewRC if this returns true
208 const TargetRegisterClass *DstRC,
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| ARMBaseRegisterInfo.cpp | 857 const TargetRegisterClass *DstRC,
869 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
878 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 159 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
164 DstRC = MRI->getRegClass(VRBase);
168 DstRC = UseRC;
170 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
179 VRBase = MRI->createVirtualRegister(DstRC);
614 const TargetRegisterClass *DstRC =
616 Register NewVReg = MRI->createVirtualRegister(DstRC);
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