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    Searched refs:DstRegs (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
CallLowering.cpp 239 void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
242 assert(DstRegs.size() > 1 && "Nothing to unpack");
249 assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
251 for (unsigned i = 0; i < DstRegs.size(); ++i)
252 MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
255 /// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
257 mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
260 LLT LLTy = MRI.getType(DstRegs[0]);
267 assert(DstRegs.size() == 1);
268 return B.buildConcatVectors(DstRegs[0], SrcRegs)
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LegalizerHelper.cpp 813 SmallVector<Register, 2> DstRegs;
815 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));
818 MIRBuilder.buildBuildVector(DstReg, DstRegs);
820 MIRBuilder.buildMerge(DstReg, DstRegs);
1031 SmallVector<Register, 2> DstRegs(NumParts);
1043 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
1045 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
1050 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1136 SmallVector<Register, 2> DstRegs;
1159 DstRegs.push_back(SrcRegs[i])
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IRTranslator.cpp 1380 auto &DstRegs = allocateVRegs(U);
1382 for (unsigned i = 0; i < DstRegs.size(); ++i)
1383 DstRegs[i] = SrcRegs[Idx++];
1392 auto &DstRegs = allocateVRegs(U);
1398 for (unsigned i = 0; i < DstRegs.size(); ++i) {
1400 DstRegs[i] = *InsertedIt++;
1402 DstRegs[i] = SrcRegs[i];
2811 const ArrayRef<Register> DstRegs = getOrCreateVRegs(U);
2814 assert(DstRegs.size() == SrcRegs.size() &&
2817 for (unsigned I = 0; I < DstRegs.size(); ++I)
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizationArtifactCombiner.h 425 SmallVector<Register, 8> DstRegs(NewNumDefs);
428 DstRegs[Idx] = MI.getOperand(Idx).getReg();
430 DstRegs[Idx] = MRI.createGenericVirtualRegister(DestTy);
435 Builder.buildUnmerge(DstRegs, CastSrcReg);
436 UpdatedDefs.append(DstRegs.begin(), DstRegs.begin() + NewNumDefs);
628 SmallVector<Register, 8> DstRegs;
631 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
662 Builder.buildInstr(ConvertOp, {DstRegs[k]}, {TmpRegs[k]});
664 Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg())
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CallLowering.h 355 /// Generate instructions for unpacking \p SrcReg into the \p DstRegs
358 /// \param DstRegs should contain one virtual register for each base type in
360 void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
LegalizerHelper.h 246 void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ControlFlowFinalizer.cpp 266 std::set<unsigned> &DstRegs) const {
293 if ((DstRegs.find(SrcMI) == DstRegs.end())) {
294 DstRegs.insert(DstMI);
307 std::set<unsigned> DstRegs;
316 if (!isCompatibleWithClause(*I, DstRegs))
AMDGPURegisterBankInfo.cpp 1939 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
1940 unsigned NumLanes = DstRegs.size();
1944 EltTy = MRI.getType(DstRegs[0]);
1969 Register DstReg = (NumLanes == 1) ? MI.getOperand(0).getReg() : DstRegs[L];
2383 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2389 B.buildCopy(DstRegs[0], SrcRegs[0]);
2392 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt);
2395 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
2398 B.buildCopy(DstRegs[0], SrcRegs[0])
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 1025 SmallSet<unsigned, 4> DstRegs;
1032 assert(!DstRegs.count(Src) && "destructive vector copy");
1033 DstRegs.insert(Dst);
1676 Register DstRegS = MI.getOperand(0).getReg();
1678 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1682 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,

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