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    Searched refs:DstVec (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 443 Register DstVec = DstIsLeft ? Left : Right;
452 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane);
462 Register DstVec, SrcVec;
464 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo;
468 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst);
AArch64InstructionSelector.cpp 4847 Register DstVec = ScalarToVec->getOperand(0).getReg();
4856 PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
4858 DstVec = PrevMI->getOperand(0).getReg();
4862 // from DstVec to the last register we've defined.
4866 getMinClassForRegBank(*RBI.getRegBank(DstVec, MRI, TRI), DstSize);
4886 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
Verifier.cpp 2926 bool DstVec = DestTy->isVectorTy();
2928 Assert(SrcVec == DstVec,
2935 if (SrcVec && DstVec)
2949 bool DstVec = DestTy->isVectorTy();
2951 Assert(SrcVec == DstVec,
2958 if (SrcVec && DstVec)
2972 bool DstVec = DestTy->isVectorTy();
2974 Assert(SrcVec == DstVec,
2981 if (SrcVec && DstVec)
2995 bool DstVec = DestTy->isVectorTy()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 9230 SDValue DstVec;
9237 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH);
9242 DstVec = DAG.getBitcast(VecVT, Imm);
9243 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec,
9247 DstVec = DAG.getUNDEF(VT);
9251 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
9255 return DstVec;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 9124 SDValue DstVec = DstIsLeft ? V1 : V2;
9141 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,

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