HomeSort by: relevance | last modified time | path
    Searched refs:EDP (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/dev/pcmcia/
if_xi.c 453 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP,
456 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP);
801 bus_space_write_2(bst, bsh, EDP, (uint16_t)len + pad);
804 bus_space_write_multi_2(bst, bsh, EDP,
808 bus_space_write_1(bst, bsh, EDP,
818 bus_space_write_2(bst, bsh, EDP, 0);
820 bus_space_write_1(bst, bsh, EDP, 0);
if_xireg.h 86 #define EDP 0x4 /* RW - Ethernet data port, 4 registers */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
rk3288.dtsi 763 * *_EDP* EDP
884 edp_phy: edp-phy {
1175 edp: dp@ff970000 { label
1601 edp {
1602 edp_hpd: edp-hpd {
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_display.c 1147 * FDI is never fed from EDP transcoder
6792 * between eDP port A enable and vdd enable. Also PCH port
8242 /* See eDP HDMI DPIO driver vbios notes doc */
8650 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8652 * documented on the DDI_FUNC_CTL register description, EDP Input Select
9480 /* Enable CPU source on CPU attached eDP */
9483 DRM_DEBUG_KMS("Using SSC on eDP\n");
10134 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
10722 * The pipe->transcoder mapping is fixed with the exception of the eDP
10779 * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI
    [all...]

Completed in 33 milliseconds