| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| ep7211-edb7211.dts | 59 regulator-name = "BACKLIGHT ENABLE";
67 regulator-name = "BACKLIGHT ENABLE";
95 line-name = "LCD ENABLE";
|
| pxa300-raumfeld-speaker-one.dts | 31 enable-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>;
129 MFP_PIN_PXA300(111) MFP_AF0 /* ENABLE */
|
| vf610-bk4.dts | 321 /* SPI ENABLE */
334 /* SDHC Enable */
|
| /src/sys/arch/luna68k/dev/ |
| lcd.c | 57 #define ENABLE 0x80
289 p1->portC = POWER | READ_BUSY | ENABLE;
293 msb = p1->portA & ENABLE;
313 p1->portC = POWER | WRITE_DATA | ENABLE;
330 p1->portC = POWER | WRITE_CMD | ENABLE;
|
| /src/sys/altq/ |
| altq_wfq.h | 99 #define ENABLE 0
|
| altq_cbq.h | 196 #define ENABLE 0x01
|
| altq_wfq.c | 100 case ENABLE:
693 error = wfq_setenable((struct wfq_interface *)addr, ENABLE);
|
| altq_cbq.c | 814 * ioctl request to enable class based queueing. It searches the list
823 cbq_set_enable(struct cbq_interface *ep, int enable)
833 switch (enable) {
834 case ENABLE:
1025 error = cbq_set_enable((struct cbq_interface *)addr, ENABLE);
|
| /src/sys/arch/hpcmips/dev/ |
| mq200debug.c | 53 #define ENABLE(b) ((b)?"enable":"disable")
263 ENABLE(reg & MQ200_GCC_ENABLE),
270 ENABLE(reg & MQ200_GCC_WINEN),
273 ENABLE(reg & MQ200_GCC_ALTEN),
287 ENABLE(reg&MQ200_GC1CRTC_DACEN));
534 ENABLE(reg & MQ200_FPC_ENABLE),
|
| /src/sys/dev/ic/ |
| aic77xx.c | 126 * Enable the board's BUS drivers
128 ahc_outb(ahc, BCTL, ENABLE);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_smu_v11_0_i2c.c | 67 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
71 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
249 /* Enable I2C */
341 /* Enable I2C */
409 /* Enable I2C engine; */
410 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
433 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
440 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
490 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
|
| amdgpu_tonga_ih.c | 59 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
63 * Enable the interrupt ring buffer (VI).
97 * tonga_ih_irq_init - init and enable the interrupt ring
102 * enable the RLC, disable interrupts, enable the IH
103 * ring buffer and enable it (VI).
155 ENABLE, 1);
158 ENABLE, 0);
164 /* enable interrupts */
|
| amdgpu_navi10_ih.c | 44 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer
48 * Enable the interrupt ring buffer (NAVI10).
105 * navi10_ih_irq_init - init and enable the interrupt ring
110 * enable the RLC, disable interrupts, enable the IH
111 * ring buffer and enable it (NAVI).
162 IH_DOORBELL_RPTR, ENABLE, 1);
165 IH_DOORBELL_RPTR, ENABLE, 0);
183 /* enable interrupts */
404 bool enable)
[all...] |
| amdgpu_amdkfd_arcturus.c | 165 ENABLE, 1);
|
| amdgpu_vega10_ih.c | 46 * vega10_ih_enable_interrupts - Enable the interrupt ring buffer
50 * Enable the interrupt ring buffer (VEGA10).
204 ENABLE, 1);
208 ENABLE, 0);
214 * vega10_ih_irq_init - init and enable the interrupt ring
219 * enable the RLC, disable interrupts, enable the IH
220 * ring buffer and enable it (VI).
349 /* enable interrupts */
686 bool enable)
[all...] |
| amdgpu_sdma_v3_0.c | 558 * @enable: enable/disable the DMA MEs context switch.
562 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
593 if (enable) {
619 * @enable: enable/disable the DMA MEs.
623 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
628 if (!enable) {
635 if (enable)
648 * Set up the gfx DMA ring buffers and enable them (VI)
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 463 ENABLE, 1);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| link_encoder.h | 77 unsigned char ENABLE : 1;
175 bool enable);
|
| /src/sys/arch/arm/nxp/ |
| imx6sx_clk.c | 1239 CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE),
1240 CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE),
1241 CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE),
1242 CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE),
1243 CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE),
1244 CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE),
1245 CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE),
|
| imx6_clk.c | 1131 CLK_GATE("pll1_sys", "pll1_bypass", CCM_ANALOG, PLL_ARM, ENABLE),
1132 CLK_GATE("pll2_bus", "pll2_bypass", CCM_ANALOG, PLL_SYS, ENABLE),
1133 CLK_GATE("pll3_usb_otg", "pll3_bypass", CCM_ANALOG, PLL_USB1, ENABLE),
1134 CLK_GATE("pll4_audio", "pll4_bypass", CCM_ANALOG, PLL_AUDIO, ENABLE),
1135 CLK_GATE("pll5_video", "pll5_bypass", CCM_ANALOG, PLL_VIDEO, ENABLE),
1136 CLK_GATE("pll6_enet", "pll6_bypass", CCM_ANALOG, PLL_ENET, ENABLE),
1137 CLK_GATE("pll7_usb_host", "pll7_bypass", CCM_ANALOG, PLL_USB2, ENABLE),
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv6xxd.h | 199 # define ENABLE (1 << 0)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_mem_input.c | 614 uint32_t enable = (total_stream_num > 1) ? 0 : local in function:dce_mi_allocate_dmif
618 ENABLE, enable);
644 uint32_t enable = (total_stream_num > 1) ? 0 : local in function:dce_mi_free_dmif
648 ENABLE, enable);
|
| dce_mem_input.h | 313 type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
|
| /src/sys/arch/mac68k/obio/ |
| iwm.s | 242 tstb %a0@(mtrOff) | ENABLE; make sure drive is off
328 tstb %a0@(mtrOn) | ENABLE; activate drive
398 tstb %a0@(mtrOn) | ENABLE; activate drive
1060 tstb %a0@(q6H) | Enable writing to disk
1364 tstb %a0@(mtrOn) | ENABLE; turn drive on
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| amdgpu_dce100_resource.c | 537 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
542 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
|
