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Searched refs:ETH_CTL_ISR (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`87 #define ETH_CTL_ISR 0x040U /* 1 = increment statistics registers */`
at91emac.c	`472 EMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 709 EMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR`
/src/sys/dev/cadence/
cemacreg.h	`129 #define ETH_CTL_ISR __BIT(6) /* 1 = increment statistics registers */`
if_cemac.c	`630 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 1019 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR`

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