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Searched refs:ETH_CTL_RE (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`91 #define ETH_CTL_RE 0x004U /* 1 = receive enable */`
at91emac.c	`233 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver 235 EMAC_WRITE(ETH_CTL, ctl \| ETH_CTL_RE); // re-enable receiver 472 EMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 709 EMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 763 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 863 EMAC_WRITE(ETH_CTL, ctl \| ETH_CTL_RE);`
/src/sys/dev/cadence/
if_cemac.c	`293 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 297 CEMAC_WRITE(ETH_CTL, ctl \| ETH_CTL_RE); 630 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 1019 CEMAC_WRITE(ETH_CTL, ETH_CTL_TE \| ETH_CTL_RE \| ETH_CTL_ISR 1096 CEMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); 1200 CEMAC_WRITE(ETH_CTL, ctl \| ETH_CTL_RE);`
cemacreg.h	`133 #define ETH_CTL_RE __BIT(2) /* 1 = receive enable */`

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