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Searched refs:ETH_IDR (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`46 #define ETH_IDR 0x2CU /* 0x2C: Interrupt Disable Register */`
at91emac.c	`145 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 200 /EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);/ 331 EMAC_WRITE(ETH_IDR, -1); // disable interrupts 466 EMAC_WRITE(ETH_IDR, -1); 704 EMAC_WRITE(ETH_IDR, -1); 727 EMAC_WRITE(ETH_IDR, -1); // disable interrupts`
/src/sys/dev/cadence/
cemacreg.h	`50 #define ETH_IDR 0x2CU /* Interrupt Disable Register */`
if_cemac.c	`169 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 239 /CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);/ 437 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts 624 CEMAC_WRITE(ETH_IDR, -1); 1014 CEMAC_WRITE(ETH_IDR, -1); 1054 CEMAC_WRITE(ETH_IDR, -1); // disable interrupts`

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