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Searched refs:ETH_IER (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`45 #define ETH_IER 0x28U /* 0x28: Interrupt Enable Register */`
at91emac.c	`467 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE 605 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 705 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE`
/src/sys/dev/cadence/
cemacreg.h	`49 #define ETH_IER 0x28U /* Interrupt Enable Register */`
if_cemac.c	`625 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE 879 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 1015 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE`

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