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Searched refs:ETH_ISR (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`44 #define ETH_ISR 0x24U /* 0x24: Interrupt Status Register */`
at91emac.c	`150 //(void)EMAC_READ(ETH_ISR); 221 isr = EMAC_READ(ETH_ISR) & imr; 336 // (void)EMAC_READ(ETH_ISR); 469 // (void)EMAC_READ(ETH_ISR); // why 732 // (void)EMAC_READ(ETH_ISR);`
/src/sys/dev/cadence/
cemacreg.h	`48 #define ETH_ISR 0x24U /* Interrupt Status Register */`
if_cemac.c	`179 //(void)CEMAC_READ(ETH_ISR); 270 isr = CEMAC_READ(ETH_ISR); 271 CEMAC_WRITE(ETH_ISR, isr); 455 // (void)CEMAC_READ(ETH_ISR); 627 // (void)CEMAC_READ(ETH_ISR); // why 1063 // (void)CEMAC_READ(ETH_ISR);`

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