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Searched refs:ETH_ISR_TBRE (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`150 #define ETH_ISR_TBRE 0x0040U /* 1 = transmit buffer register empty */`
at91emac.c	`200 /EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);/ 215 if (!(imr & (ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE 467 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE 605 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 705 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE`
/src/sys/dev/cadence/
cemacreg.h	`206 #define ETH_ISR_TBRE __BIT(6) /* 1 = transmit buffer register empty */`
if_cemac.c	`239 /CEMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);/ 263 if (!(imr & (ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE \| 625 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE 879 CEMAC_WRITE(ETH_IER, ETH_ISR_TBRE); 1015 CEMAC_WRITE(ETH_IER, ETH_ISR_RCOM \| ETH_ISR_TBRE \| ETH_ISR_TIDLE`

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