HomeSort by: relevance | last modified time | path
    Searched refs:ETH_RSR (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/at91/
at91emac.c 155 u = EMAC_READ(ETH_RSR);
156 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
225 EMAC_READ(ETH_RSR); // get receive status register
231 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
234 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
241 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
341 u = EMAC_READ(ETH_RSR);
342 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
737 u = EMAC_READ(ETH_RSR);
738 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)))
    [all...]
at91emacreg.h 43 #define ETH_RSR 0x20U /* 0x20: Receive Status Register */
  /src/sys/dev/cadence/
if_cemac.c 184 u = CEMAC_READ(ETH_RSR);
185 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
280 rsr = CEMAC_READ(ETH_RSR); // get receive status register
289 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);
295 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA);
305 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR);
460 u = CEMAC_READ(ETH_RSR);
461 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
1068 u = CEMAC_READ(ETH_RSR);
1069 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)))
    [all...]
cemacreg.h 47 #define ETH_RSR 0x20U /* Receive Status Register */

Completed in 13 milliseconds