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    Searched refs:ETH_SR_IDLE (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/arch/arm/at91/
at91emacreg.h 118 #define ETH_SR_IDLE 0x0004U /* 1 = PHY logic is running */
at91emac.c 506 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
525 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
  /src/sys/dev/cadence/
cemacreg.h 173 #define ETH_SR_IDLE __BIT(2) /* 1 = PHY logic is running */
if_cemac.c 692 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE))
709 while (!(CEMAC_READ(ETH_SR) & ETH_SR_IDLE))

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