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Searched refs:ETH_TSR (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emac.c	`151 u = EMAC_READ(ETH_TSR); 152 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 176 tsr = EMAC_READ(ETH_TSR); 337 u = EMAC_READ(ETH_TSR); 338 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 733 u = EMAC_READ(ETH_TSR); 734 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`
at91emacreg.h	`41 #define ETH_TSR 0x14U /* 0x14: Transmit Status Register */`
/src/sys/dev/cadence/
if_cemac.c	`180 u = CEMAC_READ(ETH_TSR); 181 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 203 tsr = CEMAC_READ(ETH_TSR); 212 CEMAC_WRITE(ETH_TSR, tsr); 456 u = CEMAC_READ(ETH_TSR); 457 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 1064 u = CEMAC_READ(ETH_TSR); 1065 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`
cemacreg.h	`44 #define ETH_TSR 0x14U /* Transmit Status Register */`

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