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Searched refs:ETH_TSR_BNQ (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`131 #define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued */`
at91emac.c	`152 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 177 if (!(tsr & ETH_TSR_BNQ)) { 338 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 734 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`
/src/sys/dev/cadence/
cemacreg.h	`186 #define ETH_TSR_BNQ __BIT(4) /* 1 = transmit buffer not queued (at91rm9200 only) */`
if_cemac.c	`181 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 206 if (!(tsr & ETH_TSR_BNQ)) 457 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 1065 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`

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