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Searched refs:ETH_TSR_COMP (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/arm/at91/
at91emacreg.h	`130 #define ETH_TSR_COMP 0x20U /* 1 = transmit complete */`
at91emac.c	`153 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 346 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 742 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`
/src/sys/dev/cadence/
cemacreg.h	`185 #define ETH_TSR_COMP __BIT(5) /* 1 = transmit complete */`
if_cemac.c	`181 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 465 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ 1073 CEMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND \| ETH_TSR_COMP \| ETH_TSR_BNQ`

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