| /src/external/gpl3/binutils/dist/opcodes/ |
| alpha-opc.c | 42 The information for the post-ev5 architecture extensions BWX, CIX and
52 The information for the EV5 PALcode instructions was compiled from
311 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
315 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
404 #define EV5 AXP_OPCODE_EV5
1059 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1081 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1084 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1086 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1088 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| alpha-opc.c | 42 The information for the post-ev5 architecture extensions BWX, CIX and
52 The information for the EV5 PALcode instructions was compiled from
311 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
315 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
404 #define EV5 AXP_OPCODE_EV5
1059 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1081 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1084 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1086 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1088 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| alpha-opc.c | 42 The information for the post-ev5 architecture extensions BWX, CIX and
52 The information for the EV5 PALcode instructions was compiled from
311 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
315 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
404 #define EV5 AXP_OPCODE_EV5
1059 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1081 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1084 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1086 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1088 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| alpha-opc.c | 42 The information for the post-ev5 architecture extensions BWX, CIX and
52 The information for the EV5 PALcode instructions was compiled from
311 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
315 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
404 #define EV5 AXP_OPCODE_EV5
1059 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1081 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1084 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1086 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1088 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }
[all...] |
| /src/external/lgpl3/gmp/dist/mpn/alpha/ |
| copyd.asm | 35 C EV5: 1.75
|
| copyi.asm | 35 C EV5: 1.75
|
| invert_limb.asm | 35 C EV5: 137/140 (with BWX/without BWX)
|
| sqr_diag_addlsh1.asm | 35 C EV5: 10.2
38 C Ideally, one-way code could run at 9 c/l (limited by mulq+umulh) on ev5 and
|
| addmul_1.asm | 36 C EV5: 18
|
| aorslsh1_n.asm | 35 C EV5: 6.25
|
| aorslsh2_n.asm | 35 C EV5: 6
39 C * Tune to reach 3.5 c/l on ev6 and 5.75 c/l on ev5.
|
| mod_34lsub1.asm | 35 C EV5: 2.67
|
| mul_1.asm | 36 C EV5: 18
|
| rshift.asm | 35 C EV5: 3.25
|
| sec_tabselect.asm | 37 C EV5: 2.25
|
| submul_1.asm | 36 C EV5: 18
|
| add_n.asm | 36 C EV5: 4.75
|
| com.asm | 36 C EV5: 2.0
42 C For ev5 the main loop is 7 cycles plus 1 taken branch bubble, for a total
|
| lshift.asm | 35 C EV5: 3.25
|
| mode1o.asm | 36 C EV5: 30
46 C ev4 ev5 ev6
79 C ev5. A call to gcc __remqu might be a possibility.
|
| sub_n.asm | 36 C EV5: 4.75
|
| bdiv_dbm1c.asm | 35 C EV5: 18
|
| /src/external/lgpl3/gmp/dist/mpn/alpha/ev6/ |
| aorslsh1_n.asm | 35 C EV5: 7
|
| /src/external/lgpl3/gmp/dist/mpn/alpha/ev5/ |
| diveby3.asm | 35 C EV5: 11.5
|
| /src/crypto/external/bsd/openssl.old/dist/ |
| config | 515 EV5|EV45) __CNF_CFLAGS="$__CNF_CFLAGS -mcpu=ev5"
516 __CNF_CXXFLAGS="$__CNF_CFLAGS -mcpu=ev5";;
|
