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Searched refs:EVERGREEN_CRTC0_REGISTER_OFFSET (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
evergreen_reg.h	`226 #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)`
radeon_display.c	`1502 EVERGREEN_CRTC0_REGISTER_OFFSET, 1828 EVERGREEN_CRTC0_REGISTER_OFFSET); 1830 EVERGREEN_CRTC0_REGISTER_OFFSET);`
radeon_dp_mst.c	`22 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,`
radeon_cik.c	6909 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 6921 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 7261 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 7273 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 7326 EVERGREEN_CRTC0_REGISTER_OFFSET); 7343 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, 7349 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 7351 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
radeon_device.c	`707 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) \|`
radeon_evergreen_cs.c	`1058 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET, 1066 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,`
radeon_atombios_crtc.c	`2254 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;`
radeon_evergreen.c	`122 EVERGREEN_CRTC0_REGISTER_OFFSET,`
radeon_si.c	`155 EVERGREEN_CRTC0_REGISTER_OFFSET,`
/src/sys/dev/pci/
radeonfbreg.h	`4343 #define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)`

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