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    Searched refs:EVERGREEN_CRTC_CONTROL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
evergreen_reg.h 235 #define EVERGREEN_CRTC_CONTROL 0x6e70
radeon_device.c 707 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
708 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
710 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
711 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
714 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
715 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
radeon_evergreen.c 1392 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
1687 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1689 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1712 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1714 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
2684 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
2697 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2702 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2726 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2728 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h 2018 #define EVERGREEN_CRTC_CONTROL 0x1b9c
2359 #define EVERGREEN_CRTC_CONTROL 0x1b9c
  /src/sys/dev/pci/
radeonfbreg.h 4351 #define EVERGREEN_CRTC_CONTROL 0x6e70

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