| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 1319 /// EXTLOAD is used for two things: floating point extending loads and
1321 enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD };
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| BasicTTIImpl.h | 1104 LA = getTLI()->getLoadExtAction(ISD::EXTLOAD, LT.second, MemVT);
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| SelectionDAGNodes.h | 2678 /// Returns true if the specified node is a EXTLOAD.
2681 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 120 // There are no 64-bit extloads. These should be done as a 32-bit extload and
123 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
155 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
158 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v3i16, Expand)
[all...] |
| R600ISelLowering.cpp | 48 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
59 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
60 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
61 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
65 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
69 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1417 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT,
1531 // FIXME: This should really check the extload type, but the handling of
1532 // extload vector parameters seems to be broken.
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 694 case ISD::EXTLOAD: OS << ", anyext"; break;
726 case ISD::EXTLOAD: OS << ", anyext"; break;
763 case ISD::EXTLOAD: OS << ", anyext"; break;
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| LegalizeDAG.cpp | 314 // Only do this if the target has a native EXTLOAD instruction from
316 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
331 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
370 // with a "move to register" or "extload into register" instruction, then
732 // that these bits are zero. It is also useful for EXTLOAD, since it
740 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
772 assert(!SrcVT.isVector() && "Unsupported extload!");
789 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16
[all...] |
| DAGCombiner.cpp | 379 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
673 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
794 SDValue OrigLoad, SDValue ExtLoad,
1193 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1196 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1202 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1213 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1450 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
5293 // If the load that we're shrinking is an extload and we're not just
5613 if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &
[all...] |
| LegalizeIntegerTypes.cpp | 686 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
705 N->getAddressingMode(), ISD::EXTLOAD);
720 ExtType = ISD::EXTLOAD;
3210 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
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| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 433 // Turn FP extload into load/fpextend
434 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
435 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
436 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
437 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
438 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
439 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
440 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
441 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
442 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 124 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
452 DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, HighAddr,
954 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
960 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
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| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 122 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
267 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
275 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
281 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1603 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1607 // Turn FP extload into load/fpextend.
1609 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1661 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1680 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1683 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
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| HexagonISelDAGToDAG.cpp | 77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1444 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1448 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1468 // Turn FP extload into load/fpextend
1470 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1471 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1472 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 313 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
321 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
322 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
329 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
491 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
2704 // (set dst, (i64 (extload baseptr)))
2709 (ExtType == ISD::EXTLOAD))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 180 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
181 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
186 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
189 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
828 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
1119 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
6147 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
7666 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
13587 return LD->getExtensionType() == ISD::EXTLOAD &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 166 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
347 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
351 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
457 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand);
532 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand);
591 // Sets common extload/truncstore actions on RVV floating-point vector
597 setLoadExtAction(ISD::EXTLOAD, VT, SmallVT, Expand);
628 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand);
740 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 103 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
107 // VE doesn't have floating point extload/truncstore, so expand them.
110 setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 1000 (Load->getExtensionType() == ISD::EXTLOAD ||
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| SystemZISelLowering.cpp | 301 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
335 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
613 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
617 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f32, Expand);
618 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
3872 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
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