| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 531 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
543 EXTRACT_SUBVECTOR,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 330 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
331 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
332 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom);
333 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom);
334 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
335 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
336 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom);
337 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom);
338 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
339 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom)
[all...] |
| SIISelLowering.cpp | 258 case ISD::EXTRACT_SUBVECTOR:
581 case ISD::EXTRACT_SUBVECTOR:
1649 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
5525 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
5528 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
5531 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
5540 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
922 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
1262 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
1265 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
2156 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
2425 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
2427 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
2784 // %inlo = v4i32 extract_subvector %in, 0
2785 // %inhi = v4i32 extract_subvector %in, 4
2984 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break
[all...] |
| DAGCombiner.cpp | 655 case ISD::EXTRACT_SUBVECTOR:
1714 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
12268 // fold (truncate (extract_subvector(ext x))) ->
12269 // (extract_subvector x)
12272 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
12279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT,
15621 // TODO: Support vectors? This requires extract_subvector/bitcast.
16785 // EXTRACT_SUBVECTOR.
16788 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
16794 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR
[all...] |
| SelectionDAGDumper.cpp | 288 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector";
|
| SelectionDAG.cpp | 2550 case ISD::EXTRACT_SUBVECTOR: {
2898 case ISD::EXTRACT_SUBVECTOR: {
4094 case ISD::EXTRACT_SUBVECTOR: {
4511 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
5800 // EXTRACT_VECTOR_ELT of v1iX EXTRACT_SUBVECTOR could be formed
5802 // vextract (v1iX extract_subvector(vNiX, Idx)) -> vextract(vNiX,Idx).
5808 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
5836 case ISD::EXTRACT_SUBVECTOR:
5854 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
5860 // EXTRACT_SUBVECTOR of an UNDEF is an UNDEF
[all...] |
| LegalizeIntegerTypes.cpp | 97 case ISD::EXTRACT_SUBVECTOR:
426 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
1273 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1521 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
4668 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops);
4912 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
|
| SelectionDAGBuilder.cpp | 412 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
747 // definition of EXTRACT_SUBVECTOR for further details.
750 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
3652 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result,
3697 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src,
7145 setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index));
|
| LegalizeDAG.cpp | 2981 case ISD::EXTRACT_SUBVECTOR:
|
| TargetLowering.cpp | 1084 case ISD::EXTRACT_SUBVECTOR: {
2616 case ISD::EXTRACT_SUBVECTOR: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
1410 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1506 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1720 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1881 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
2011 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
4916 if (Opcode == ISD::EXTRACT_SUBVECTOR)
5259 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() ||
5331 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
5893 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 123 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom);
227 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom);
1968 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy,
2050 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResTy,
2104 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG);
|
| HexagonISelLowering.cpp | 1648 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1697 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
3140 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 155 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR);
2085 // Combine ({s,z}ext (extract_subvector src, i)) into a widening operation if
2086 // possible before the extract_subvector can be expanded.
2088 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
2139 // (v2i32 (extract_subvector (v4i32 $x), 0))))
2143 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
2160 } else if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
2163 // (v2f64 (extract_subvector
2247 case ISD::EXTRACT_SUBVECTOR:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 1170 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1381 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1440 // We use EXTRACT_SUBVECTOR to "cast" a scalable vector to a fixed length one.
1441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
4407 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl,
4411 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl,
4564 case ISD::EXTRACT_SUBVECTOR:
8309 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8315 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8320 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec
[all...] |
| AArch64ISelDAGToDAG.cpp | 612 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
2039 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
3439 case ISD::EXTRACT_SUBVECTOR: {
3440 // Bail when not a "cast" like extract_subvector.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
522 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
586 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
633 // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
635 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
744 // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed.
746 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1272 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero);
1421 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec,
1727 // FIXME: Peek through INSERT_SUBVECTOR, EXTRACT_SUBVECTOR, bitcasts
[all...] |
| RISCVISelDAGToDAG.cpp | 1096 case ISD::EXTRACT_SUBVECTOR: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 186 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
441 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
5930 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
7834 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7840 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7845 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7848 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
8727 "Unexpected custom EXTRACT_SUBVECTOR lowering");
8729 "EXTRACT_SUBVECTOR lowering only supported for MVE");
9144 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 2167 case ISD::EXTRACT_SUBVECTOR:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 7756 Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1,
7758 Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1,
10718 case ISD::EXTRACT_SUBVECTOR: {
|
