| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 181 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
182 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
184 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
251 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
452 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
545 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
547 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
549 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
551 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2)
[all...] |
| SIISelLowering.cpp | 255 case ISD::EXTRACT_VECTOR_ELT:
282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
283 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
296 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
297 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v8i32);
310 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
311 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v16i32);
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
325 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32);
349 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom)
[all...] |
| AMDGPUISelLowering.cpp | 1462 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1463 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1473 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
1481 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
1513 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL,
2165 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2350 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2351 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2491 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2493 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC
[all...] |
| AMDGPUISelDAGToDAG.cpp | 320 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
348 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
924 // (or (extract_vector_elt V, 0), OFFSET),
925 // (extract_vector_elt V, 1)))))
931 if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
932 BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 496 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
505 EXTRACT_VECTOR_ELT,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
330 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
388 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
413 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
450 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
545 ISD::EXTRACT_VECTOR_ELT, dl, SrcVT.getVectorElementType(), Src,
568 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
570 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
625 case ISD::EXTRACT_VECTOR_ELT:
1494 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT
[all...] |
| LegalizeTypesGeneric.cpp | 125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT,
222 // The result of EXTRACT_VECTOR_ELT may be larger than the element type of
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
|
| LegalizeVectorOps.cpp | 1486 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1525 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1527 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
|
| LegalizeDAG.cpp | 1003 case ISD::EXTRACT_VECTOR_ELT:
1324 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
2972 case ISD::EXTRACT_VECTOR_ELT:
3058 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3062 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(),
3756 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(),
4378 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4793 case ISD::EXTRACT_VECTOR_ELT: {
4799 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i3
[all...] |
| LegalizeFloatTypes.cpp | 65 case ISD::EXTRACT_VECTOR_ELT:
247 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
1182 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2221 case ISD::EXTRACT_VECTOR_ELT:
2375 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
2583 case ISD::EXTRACT_VECTOR_ELT:
2665 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
|
| DAGCombiner.cpp | 368 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
371 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
654 case ISD::EXTRACT_VECTOR_ELT:
1711 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
5702 // the 'X' node here can either be nothing or an extract_vector_elt to catch
5704 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
12041 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
12045 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
12050 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
12069 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy
[all...] |
| SelectionDAGDumper.cpp | 285 case ISD::EXTRACT_VECTOR_ELT: return "extract_vector_elt";
|
| LegalizeIntegerTypes.cpp | 69 case ISD::EXTRACT_VECTOR_ELT:
577 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
1492 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
2067 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
4690 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4824 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
4897 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4900 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
4948 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 373 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
1883 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1931 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
1933 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector,
2169 case ISD::EXTRACT_VECTOR_ELT:
2357 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2359 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2367 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
2581 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P,
4857 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1420 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
1499 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1729 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1871 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
2008 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 171 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
263 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
444 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
982 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
2366 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2368 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3048 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3067 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 185 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT})
1243 case ISD::EXTRACT_VECTOR_ELT:
1643 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1668 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(),
1697 // (extract_vector_elt
1699 // (sign_extend_inreg (extract_vector_elt $indices, $i))
1703 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1710 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1726 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
|
| /src/external/apache2/llvm/dist/llvm/utils/ |
| update_mir_test_checks.py | 259 EXTRACT_VECTOR_ELT='EVEC',
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 1053 if (ISD == ISD::EXTRACT_VECTOR_ELT &&
1101 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 124 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
228 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom);
565 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1276 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1278 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy,
2105 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
501 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
502 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
646 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
4626 // of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
4934 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
4942 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
4952 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5262 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 909 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1185 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1377 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
4359 SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
4556 case ISD::EXTRACT_VECTOR_ELT:
8224 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
8371 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
9142 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
9760 // 5) if all operands are EXTRACT_VECTOR_ELT, check for VUZP
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 298 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal);
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalPackedVT, Custom);
1719 case ISD::EXTRACT_VECTOR_ELT:
2741 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 328 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
465 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
1782 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1783 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1797 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1798 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
2189 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT becaus
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 242 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
245 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
859 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
862 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
|
