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    Searched refs:EltSize (Results 1 - 25 of 53) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86ShuffleDecode.h 140 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
144 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
X86ShuffleDecode.cpp 398 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
408 if (0 != (Len % EltSize) || 0 != (Idx % EltSize))
422 Len /= EltSize;
423 Idx /= EltSize;
435 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
445 if (0 != (Len % EltSize) || 0 != (Idx % EltSize))
459 Len /= EltSize;
460 Idx /= EltSize;
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuilder.h 212 CharUnits EltSize =
218 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
230 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy));
234 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
245 CharUnits EltSize =
250 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
CGNonTrivialStruct.cpp 196 CharUnits EltSize = Ctx.getTypeSizeInChars(EltTy);
198 llvm::to_string(EltSize.getQuantity()) + "n" +
399 CharUnits EltSize = Ctx.getTypeSizeInChars(EltQT);
404 PHIs[I], StartAddrs[I].getAlignment().alignmentAtOffset(EltSize));
415 NewAddrs[I] = getAddrWithOffset(NewAddrs[I], EltSize);
TargetInfo.cpp 3001 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
3009 (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
3012 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
3303 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
3309 unsigned EltOffset = i*EltSize;
3391 unsigned EltSize = TD.getTypeAllocSize(EltTy);
3392 IROffset -= IROffset/EltSize*EltSize;
3481 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3482 unsigned EltOffset = IROffset/EltSize*EltSize
    [all...]
CGDecl.cpp 1736 CharUnits EltSize = getContext().getTypeSizeInChars(VlaSize.Type);
1744 if (!EltSize.isOne())
1745 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize));
1767 if (!EltSize.isOne())
1768 SizeVal = Builder.CreateNUWMul(SizeVal, CGM.getSize(EltSize));
1770 llvm::ConstantInt::get(IntPtrTy, EltSize.getQuantity());
1778 CharUnits CurAlign = Loc.getAlignment().alignmentOfArrayElement(EltSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 100 unsigned EltSize;
205 unsigned read2Opcode(unsigned EltSize) const;
206 unsigned read2ST64Opcode(unsigned EltSize) const;
211 unsigned write2Opcode(unsigned EltSize) const;
212 unsigned write2ST64Opcode(unsigned EltSize) const;
499 EltSize =
504 EltSize =
509 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4);
512 EltSize = 4;
754 if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0)
    [all...]
SIRegisterInfo.cpp 97 unsigned EltSize = 4;
119 SplitParts = TRI.getRegSplitParts(RC, EltSize);
988 unsigned EltSize) {
994 switch (EltSize) {
1048 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1049 unsigned NumSubRegs = RegWidth / EltSize;
1050 unsigned Size = NumSubRegs * EltSize;
1054 int64_t MaxOffset = Offset + Size + RemSize - EltSize;
1057 if (IsFlat && EltSize > 4) {
1058 LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize);
    [all...]
AMDGPULegalizerInfo.cpp 72 const unsigned EltSize = EltTy.getSizeInBits();
74 EltSize > 1 && EltSize < 32 &&
121 const int EltSize = EltTy.getSizeInBits();
124 assert(EltSize < 32);
126 const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize;
186 const int EltSize = EltTy.getSizeInBits();
187 return EltSize == 16 || EltSize % 32 == 0
    [all...]
AMDGPUTargetTransformInfo.cpp 887 unsigned EltSize
889 if (EltSize < 32) {
890 if (EltSize == 16 && Index == 0 && ST->has16BitInsts())
1339 unsigned EltSize
1341 if (EltSize < 32) {
SIRegisterInfo.h 242 unsigned EltSize) const;
AMDGPURegisterBankInfo.cpp 1120 unsigned EltSize = EltTy.getSizeInBits();
1121 assert(FirstSize % EltSize == 0);
1123 unsigned FirstPartNumElts = FirstSize / EltSize;
1124 unsigned RemainderElts = (TotalSize - FirstSize) / EltSize;
1752 int EltSize = Ty.getScalarSizeInBits();
1756 if (EltSize != 32)
1911 unsigned EltSize = VecTy.getScalarSizeInBits();
1914 if (!SITargetLowering::shouldExpandVectorDynExt(EltSize, NumElem,
1993 unsigned EltSize = VecTy.getScalarSizeInBits();
1996 if (!SITargetLowering::shouldExpandVectorDynExt(EltSize, NumElem
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.h 270 unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
271 return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
272 EltSize <= 128 && isPowerOf2_64(EltSize);
AArch64StackTagging.cpp 272 uint32_t EltSize = DL->getTypeSizeInBits(EltTy);
274 IntegerType::get(Ctx, EltSize),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 66 static bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts,
70 assert(EltSize != 64 && "EltSize cannot be 64 for REV mask.");
76 BlockElts = BlockSize / EltSize;
78 if (BlockSize <= EltSize || BlockSize != BlockElts * EltSize)
225 unsigned EltSize = Ty.getScalarSizeInBits();
228 if (EltSize == 64)
234 if (isREVMask(ShuffleMask, EltSize, NumElts, 64)) {
922 unsigned EltSize = MRI.getType(LHS).getScalarSizeInBits()
    [all...]
AArch64InstructionSelector.cpp 138 MachineInstr *emitScalarToVector(unsigned EltSize,
2331 unsigned EltSize = DstTy.getElementType().getSizeInBits();
2332 if (EltSize == 32)
2335 else if (EltSize == 64)
3630 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
3644 switch (EltSize) {
3726 const unsigned EltSize) {
3729 switch (EltSize) {
3744 LLVM_DEBUG(dbgs() << "Elt size '" << EltSize << "' unsupported.\n");
4064 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
Loads.cpp 279 APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()),
288 return isDereferenceableAndAlignedPointer(Ptr, Alignment, EltSize, DL,
300 if (Step->getAPInt() != EltSize)
307 const APInt AccessSize = TC * EltSize;
318 if (EltSize.urem(Alignment.value()) != 0)
ModuleSummaryAnalysis.cpp 518 uint64_t EltSize = DL.getTypeAllocSize(EltTy);
521 StartingOffset + i * EltSize, M, Index, VTableFuncs);
ConstantFolding.cpp 476 uint64_t EltSize = DL.getTypeAllocSize(CS->getOperand(Index)->getType());
478 if (ByteOffset < EltSize &&
515 uint64_t EltSize = DL.getTypeAllocSize(EltTy);
516 uint64_t Index = ByteOffset / EltSize;
517 uint64_t Offset = ByteOffset - Index * EltSize;
524 uint64_t BytesWritten = EltSize - Offset;
525 assert(BytesWritten <= EltSize && "Not indexing into this element?");
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4110 unsigned EltSize = MemIntr->getMemoryVT().getSizeInBits();
4111 assert((EltSize == 32 || EltSize == 64) && "Unexpected broadcast size!");
4113 bool UseD = EltSize == 32;
5734 unsigned EltSize = ValueSVT.getSizeInBits();
5739 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32)
5741 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 32)
5743 else if (IndexVT == MVT::v16i32 && NumElts == 16 && EltSize == 32)
5745 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64)
5747 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
Analysis.cpp 107 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue();
110 StartingOffset + i * EltSize);
152 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue();
155 StartingOffset + i * EltSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 1505 unsigned EltSize = VTy->getScalarSizeInBits();
1521 if (EltSize < 8 || Alignment < EltSize / 8)
1524 unsigned ExtSize = EltSize;
1538 if (((TypeSize == 32 && (EltSize == 8 || EltSize == 16)) ||
1539 (TypeSize == 16 && EltSize == 8)) &&
1552 if (((EltSize == 16 && TypeSize == 32) ||
1553 (EltSize == 8 && (TypeSize == 32 || TypeSize == 16))) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 1067 unsigned EltSize = Val->getScalarSizeInBits();
1068 if (EltSize == 64) {
1072 } else if (EltSize == 32) {
PPCISelLowering.h 402 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
650 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
665 unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineLoadStoreAlloca.cpp 701 auto EltSize = DL.getTypeAllocSize(ET);
724 Offset += EltSize;
1224 auto EltSize = DL.getTypeAllocSize(AT->getElementType());
1250 Offset += EltSize;

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