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      1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
      2 //
      3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
      4 // See https://llvm.org/LICENSE.txt for license information.
      5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
      6 //
      7 //===----------------------------------------------------------------------===//
      8 //
      9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
     10 //
     11 //===----------------------------------------------------------------------===//
     12 
     13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
     14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
     15 
     16 #include "MCTargetDesc/RISCVBaseInfo.h"
     17 #include "RISCVFrameLowering.h"
     18 #include "RISCVISelLowering.h"
     19 #include "RISCVInstrInfo.h"
     20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
     21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
     22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
     23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
     24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
     25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
     26 #include "llvm/IR/DataLayout.h"
     27 #include "llvm/Target/TargetMachine.h"
     28 
     29 #define GET_SUBTARGETINFO_HEADER
     30 #include "RISCVGenSubtargetInfo.inc"
     31 
     32 namespace llvm {
     33 class StringRef;
     34 
     35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
     36   virtual void anchor();
     37   bool HasStdExtM = false;
     38   bool HasStdExtA = false;
     39   bool HasStdExtF = false;
     40   bool HasStdExtD = false;
     41   bool HasStdExtC = false;
     42   bool HasStdExtB = false;
     43   bool HasStdExtZba = false;
     44   bool HasStdExtZbb = false;
     45   bool HasStdExtZbc = false;
     46   bool HasStdExtZbe = false;
     47   bool HasStdExtZbf = false;
     48   bool HasStdExtZbm = false;
     49   bool HasStdExtZbp = false;
     50   bool HasStdExtZbr = false;
     51   bool HasStdExtZbs = false;
     52   bool HasStdExtZbt = false;
     53   bool HasStdExtZbproposedc = false;
     54   bool HasStdExtV = false;
     55   bool HasStdExtZvlsseg = false;
     56   bool HasStdExtZvamo = false;
     57   bool HasStdExtZfh = false;
     58   bool HasRV64 = false;
     59   bool IsRV32E = false;
     60   bool EnableLinkerRelax = false;
     61   bool EnableRVCHintInstrs = true;
     62   bool EnableSaveRestore = false;
     63   unsigned XLen = 32;
     64   MVT XLenVT = MVT::i32;
     65   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
     66   BitVector UserReservedRegister;
     67   RISCVFrameLowering FrameLowering;
     68   RISCVInstrInfo InstrInfo;
     69   RISCVRegisterInfo RegInfo;
     70   RISCVTargetLowering TLInfo;
     71   SelectionDAGTargetInfo TSInfo;
     72 
     73   /// Initializes using the passed in CPU and feature strings so that we can
     74   /// use initializer lists for subtarget initialization.
     75   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
     76                                                   StringRef CPU,
     77                                                   StringRef TuneCPU,
     78                                                   StringRef FS,
     79                                                   StringRef ABIName);
     80 
     81 public:
     82   // Initializes the data members to match that of the specified triple.
     83   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
     84                  StringRef FS, StringRef ABIName, const TargetMachine &TM);
     85 
     86   // Parses features string setting specified subtarget options. The
     87   // definition of this function is auto-generated by tblgen.
     88   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
     89 
     90   const RISCVFrameLowering *getFrameLowering() const override {
     91     return &FrameLowering;
     92   }
     93   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
     94   const RISCVRegisterInfo *getRegisterInfo() const override {
     95     return &RegInfo;
     96   }
     97   const RISCVTargetLowering *getTargetLowering() const override {
     98     return &TLInfo;
     99   }
    100   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
    101     return &TSInfo;
    102   }
    103   bool enableMachineScheduler() const override { return true; }
    104   bool hasStdExtM() const { return HasStdExtM; }
    105   bool hasStdExtA() const { return HasStdExtA; }
    106   bool hasStdExtF() const { return HasStdExtF; }
    107   bool hasStdExtD() const { return HasStdExtD; }
    108   bool hasStdExtC() const { return HasStdExtC; }
    109   bool hasStdExtB() const { return HasStdExtB; }
    110   bool hasStdExtZba() const { return HasStdExtZba; }
    111   bool hasStdExtZbb() const { return HasStdExtZbb; }
    112   bool hasStdExtZbc() const { return HasStdExtZbc; }
    113   bool hasStdExtZbe() const { return HasStdExtZbe; }
    114   bool hasStdExtZbf() const { return HasStdExtZbf; }
    115   bool hasStdExtZbm() const { return HasStdExtZbm; }
    116   bool hasStdExtZbp() const { return HasStdExtZbp; }
    117   bool hasStdExtZbr() const { return HasStdExtZbr; }
    118   bool hasStdExtZbs() const { return HasStdExtZbs; }
    119   bool hasStdExtZbt() const { return HasStdExtZbt; }
    120   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
    121   bool hasStdExtV() const { return HasStdExtV; }
    122   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
    123   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
    124   bool hasStdExtZfh() const { return HasStdExtZfh; }
    125   bool is64Bit() const { return HasRV64; }
    126   bool isRV32E() const { return IsRV32E; }
    127   bool enableLinkerRelax() const { return EnableLinkerRelax; }
    128   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
    129   bool enableSaveRestore() const { return EnableSaveRestore; }
    130   MVT getXLenVT() const { return XLenVT; }
    131   unsigned getXLen() const { return XLen; }
    132   RISCVABI::ABI getTargetABI() const { return TargetABI; }
    133   bool isRegisterReservedByUser(Register i) const {
    134     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
    135     return UserReservedRegister[i];
    136   }
    137 
    138 protected:
    139   // GlobalISel related APIs.
    140   std::unique_ptr<CallLowering> CallLoweringInfo;
    141   std::unique_ptr<InstructionSelector> InstSelector;
    142   std::unique_ptr<LegalizerInfo> Legalizer;
    143   std::unique_ptr<RegisterBankInfo> RegBankInfo;
    144 
    145 public:
    146   const CallLowering *getCallLowering() const override;
    147   InstructionSelector *getInstructionSelector() const override;
    148   const LegalizerInfo *getLegalizerInfo() const override;
    149   const RegisterBankInfo *getRegBankInfo() const override;
    150 
    151   // Return the known range for the bit length of RVV data registers. A value
    152   // of 0 means nothing is known about that particular limit beyond what's
    153   // implied by the architecture.
    154   unsigned getMaxRVVVectorSizeInBits() const;
    155   unsigned getMinRVVVectorSizeInBits() const;
    156   unsigned getMaxLMULForFixedLengthVectors() const;
    157   bool useRVVForFixedLengthVectors() const;
    158 };
    159 } // End llvm namespace
    160 
    161 #endif
    162