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    Searched refs:ExitSU (Results 1 - 13 of 13) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MacroFusion.cpp 99 if (&SecondSU != &DAG.ExitSU)
103 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU))
121 // ExitSU comes last by design, which acts like an implicit dependency
122 // between ExitSU and any bottom root in the graph. We should transfer
124 if (&SecondSU == &DAG.ExitSU) {
161 if (DAG->ExitSU.getInstr())
162 // Try to fuse the instr in the ExitSU with one in its predecessors.
163 scheduleAdjacentImpl(*DAG, DAG->ExitSU);
ScheduleDAGInstrs.cpp 117 Type::getVoidTy(mf.getFunction().getContext()))), Topo(SUnits, &ExitSU) {
206 ExitSU.setInstr(ExitMI);
213 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
215 addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
225 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
313 if (DefSU == &ExitSU)
514 /// TODO: Handle ExitSU "uses" properly.
797 // ExitSU.
879 // dependence edge to ExitSU to model the live-out latency. This is required
887 ExitSU.addPred(Dep)
    [all...]
ScheduleDAG.cpp 67 ExitSU = SUnit();
357 else if (&SU == &ExitSU)
358 dbgs() << "ExitSU";
478 if (ExitSU)
479 WorkList.push_back(ExitSU);
583 // Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
625 // Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
748 ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits, SUnit *exitsu)
749 : SUnits(sunits), ExitSU(exitsu) {}
    [all...]
MachineScheduler.cpp 660 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
861 ExitSU.biasCriticalPath();
870 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
885 releasePredecessors(&ExitSU);
1133 if (SU.isScheduled || &SU == &ExitSU)
1167 if (!SU->isScheduled && SU != &ExitSU) {
1201 if (ExitSU.getInstr() != nullptr)
1202 dumpNodeAll(ExitSU);
1362 if (SU == &ExitSU)
1394 /// Release ExitSU predecessors and setup scheduler queues. Re-positio
    [all...]
PostRASchedulerList.cpp 481 // to be scheduled. Ignore the special ExitSU node.
482 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGVLIW.cpp 131 // to be scheduled. Ignore the special ExitSU node.
132 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
ScheduleDAGSDNodes.cpp 703 if (ExitSU.getNode() != nullptr)
704 dumpNodeAll(ExitSU);
ScheduleDAGFast.cpp 528 ReleasePredecessors(&ExitSU, CurCycle);
ScheduleDAGRRList.cpp 1599 ReleasePredecessors(&ExitSU);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAG.h 564 SUnit ExitSU; ///< Special node for the region exit.
697 SUnit *ExitSU;
730 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
MachinePipeliner.h 197 RegClassInfo(rci), II_setByPragma(II), Topo(SUnits, &ExitSU) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNILPSched.cpp 310 releasePredecessors(&DAG.ExitSU);
SIMachineScheduler.h 457 SUnit& getExitSU() { return ExitSU; }

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