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    Searched refs:Ext1 (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
VectorCombine.cpp 77 ExtractElementInst *Ext1,
79 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
83 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
85 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
234 ExtractElementInst *Ext0, ExtractElementInst *Ext1,
237 isa<ConstantInt>(Ext1->getIndexOperand()) &&
241 unsigned Index1 = cast<ConstantInt>(Ext1->getIndexOperand())->getZExtValue();
248 assert(VecTy == Ext1->getVectorOperand()->getType() && "Need matching types");
252 TTI.getVectorInstrCost(Ext1->getOpcode(), VecTy, Index1);
264 return Ext1;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/BinaryFormat/
MsgPackWriter.cpp 177 case FixLen::Ext1:
MsgPackReader.cpp 120 return createExt(Obj, FixLen::Ext1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 9689 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9695 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags());
9701 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9703 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags());
12633 SDValue Ext1 = Mul.getOperand(1);
12635 Ext1.getOpcode() != ISD::SIGN_EXTEND)
12640 if (Ext1.getOperand(0).getValueType() != VecVT ||
12647 Ext1.getOperand(0));
17294 /// Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth
17296 static bool areExtractExts(Value *Ext1, Value *Ext2)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2568 auto Ext1 = B.buildFPExt(S32, Src1, Flags);
2571 .addUse(Ext1.getReg(0))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 14009 SDValue Ext1 = FirstInput.getOperand(0);
14011 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
14015 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1));
14019 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 ||
14020 Ext1.getOperand(0) != Ext2.getOperand(0))
14033 SDValue SrcVec = Ext1.getOperand(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 11143 /// Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth
11145 static bool areExtractExts(Value *Ext1, Value *Ext2) {
11151 if (!match(Ext1, m_ZExtOrSExt(m_Value())) ||
11153 !areExtDoubled(cast<Instruction>(Ext1)) ||
11214 auto Ext1 = cast<Instruction>(I->getOperand(0));
11216 if (areExtractShuffleVectors(Ext1, Ext2)) {
11217 Ops.push_back(&Ext1->getOperandUse(0));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 10237 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1);
10239 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2);
18500 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index);
18501 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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