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    Searched refs:ExtOp (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
SCCP.cpp 169 Value *ExtOp = Inst.getOperand(0);
170 if (isa<Constant>(ExtOp) || InsertedValues.count(ExtOp))
172 const ValueLatticeElement &IV = Solver.getLatticeValueFor(ExtOp);
176 auto *ZExt = new ZExtInst(ExtOp, Inst.getType(), "", &Inst);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 4495 unsigned ExtOp, TruncOp;
4497 ExtOp = ISD::BITCAST;
4504 ExtOp = ISD::ANY_EXTEND;
4508 ExtOp = ISD::SIGN_EXTEND;
4512 ExtOp = ISD::ZERO_EXTEND;
4518 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4519 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4528 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4530 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4531 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1))
    [all...]
DAGCombiner.cpp 14549 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
14551 return DAG.getNode(ExtOp, SDLoc(N), VT, Src);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonConstExtenders.cpp 1533 MachineOperand ExtOp(EV);
1544 .add(ExtOp);
1550 .add(ExtOp);
1555 .add(ExtOp)
1561 .add(ExtOp);
1569 .add(ExtOp)
1582 .add(ExtOp)
1587 .add(ExtOp);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
BasicTTIImpl.h 1733 unsigned ExtOp =
1738 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, RetTy, CCH, CostKind);
1802 unsigned ExtOp =
1807 Cost += 2 * thisT()->getCastInstrCost(ExtOp, ExtTy, MulTy, CCH, CostKind);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
MachineIRBuilder.cpp 446 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
447 return buildInstr(ExtOp, Res, Op);
LegalizerHelper.cpp 1776 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp});
1777 // There is no overflow if the ExtOp is the same as NewOp.
1778 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
1848 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1849 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS});
1850 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS});
6784 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
6790 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)});
6791 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)});
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCodeGenPrepare.cpp 429 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty);
430 Value *ExtRes = Builder.CreateCall(I32, { ExtOp });
SIISelLowering.cpp 9873 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
9875 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
9876 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
9877 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
SimplifyIndVar.cpp 1495 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp);
1496 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 6120 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6121 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
13853 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1));
13854 if (!ExtOp)
13857 Index = ExtOp->getZExtValue();
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 6357 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
6358 return DAG.getNode(Opcode, SDLoc(N), OutVT, ExtOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 18879 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
18882 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
    [all...]
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuiltin.cpp 7074 Value *ExtOp, Value *IndexOp,
7078 if (ExtOp)
7079 TblOps.push_back(ExtOp);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 15850 SDValue ExtOp = Src->getOperand(0);
15860 SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ExtOp.getValueType(),
15861 ExtOp, DAG.getValueType(ExtVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 12076 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
12077 return DAG.getNode(ExtOp, dl, VT, tmp);

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