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    Searched refs:ExtOpcode (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
LegalizerHelper.h 121 /// ExtOpcode for the extension instruction, and replacing the vreg of the
124 unsigned ExtOpcode);
139 // extending back with \p ExtOpcode.
141 unsigned ExtOpcode);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 1255 unsigned OpIdx, unsigned ExtOpcode) {
1257 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1278 unsigned OpIdx, unsigned ExtOpcode) {
1282 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
1718 unsigned ExtOpcode;
1725 ExtOpcode = TargetOpcode::G_SEXT;
1729 ExtOpcode = TargetOpcode::G_SEXT;
1733 ExtOpcode = TargetOpcode::G_ZEXT;
1737 ExtOpcode = TargetOpcode::G_ZEXT;
1741 ExtOpcode = TargetOpcode::G_SEXT
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSelect.cpp 1923 auto ExtOpcode = ExtInst->getOpcode();
1924 if (ExtOpcode != Instruction::ZExt && ExtOpcode != Instruction::SExt)
1941 Constant *ExtC = ConstantExpr::getCast(ExtOpcode, TruncC, SelType);
1950 return CastInst::Create(Instruction::CastOps(ExtOpcode), NewSel, SelType);
1960 Constant *AllOnesOrOne = ConstantExpr::getCast(ExtOpcode, One, SelType);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPURegisterBankInfo.cpp 1610 unpackV2S16ToS32(MachineIRBuilder &B, Register Src, unsigned ExtOpcode) {
1614 if (ExtOpcode == TargetOpcode::G_SEXT) {
1621 if (ExtOpcode == TargetOpcode::G_ZEXT) {
1626 assert(ExtOpcode == TargetOpcode::G_ANYEXT);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 3501 unsigned ExtOpcode) {
3512 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
11910 unsigned ExtOpcode = Op0.getOpcode();
11913 if (ExtOpcode == ISD::MUL) {
11919 ExtOpcode = A.getOpcode();
11921 if (ExtOpcode != ISD::ZERO_EXTEND && ExtOpcode != ISD::SIGN_EXTEND)
11939 (ExtOpcode == ISD::ZERO_EXTEND) ? AArch64ISD::UDOT : AArch64ISD::SDOT;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 9926 auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
9927 SDValue WideLHS = DAG.getNode(ExtOpcode, DL, WideVT, LHS);
9928 SDValue WideRHS = DAG.getNode(ExtOpcode, DL, WideVT, RHS);
10174 /// The load is compatible with ExtOpcode. It means
10178 static bool isCompatibleLoad(SDValue N, unsigned ExtOpcode) {
10190 // Now LoadExt is either SEXTLOAD or ZEXTLOAD, ExtOpcode must have the same
10192 if ((LoadExt == ISD::SEXTLOAD && ExtOpcode != ISD::SIGN_EXTEND) ||
10193 (LoadExt == ISD::ZEXTLOAD && ExtOpcode != ISD::ZERO_EXTEND))
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 2207 unsigned ExtOpcode = Op.getOpcode() == ISD::UINT_TO_FP
2210 SDValue Ext = DAG.getNode(ExtOpcode, DL, IVecVT, Src);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 6355 unsigned ExtOpcode =
6357 SDValue ExtOp = DAG.getNode(ExtOpcode, SDLoc(N), ExtVT, Op);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 8868 unsigned ExtOpcode) {
8879 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);

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