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    Searched refs:ExtReg (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 110 Register ExtReg = extendRegister(ValVReg, VA);
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
117 Register ExtReg = extendRegister(ValVReg, VA);
122 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
X86FastISel.cpp 1097 Register ExtReg = createResultReg(&X86::GR64RegClass);
1099 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg)
1103 Reg = ExtReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 119 Register ExtReg = extendRegister(ValVReg, VA);
120 MIRBuilder.buildCopy(PhysReg, ExtReg);
129 Register ExtReg = extendRegister(ValVReg, VA);
133 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 253 Register ExtReg = extendRegister(ValVReg, VA);
254 MIRBuilder.buildCopy(PhysReg, ExtReg);
287 Register ExtReg = extendRegister(ValVReg, VA);
288 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 64 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
73 {MRI.getType(ExtReg)}, false)
74 .addReg(ExtReg);
75 ExtReg = ToSGPR.getReg(0);
78 MIRBuilder.buildCopy(PhysReg, ExtReg);
213 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
214 MIRBuilder.buildCopy(PhysReg, ExtReg);
AMDGPUInstructionSelector.cpp 2061 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
2066 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
2073 .addReg(ExtReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 931 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
934 SrcReg1 = ExtReg;
937 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
940 SrcReg2 = ExtReg;
PPCISelLowering.cpp 11075 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11077 ExtReg).addReg(dest);
11079 .addReg(incr).addReg(ExtReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 275 Register ExtReg = extendRegister(ValVReg, VA);
276 MIRBuilder.buildCopy(PhysReg, ExtReg);
AArch64InstructionSelector.cpp 5529 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(),
5533 // Base is LHS, offset is ExtReg.
5535 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); },
5832 Register ExtReg;
5859 ExtReg = ExtDef->getOperand(1).getReg();
5865 ExtReg = RootDef->getOperand(1).getReg();
5871 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) {
5872 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg);
5878 // We require a GPR32 here. Narrow the ExtReg if needed using a subregister
5881 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB)
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