HomeSort by: relevance | last modified time | path
    Searched refs:F64 (Results 1 - 22 of 22) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
WebAssemblyTypeUtilities.h 32 F64 = unsigned(wasm::ValType::F64),
WebAssemblyTypeUtilities.cpp 28 if (Type == "f64")
29 return wasm::ValType::F64;
53 .Case("f64", WebAssembly::BlockType::F64)
66 .Case("f64", MVT::f64)
88 return "f64";
135 case MVT::f64:
136 return wasm::ValType::F64;
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRuntimeLibcallSignatures.cpp 506 // consistent with the f64 and f128 names.
536 Params.push_back(wasm::ValType::F64);
551 Rets.push_back(wasm::ValType::F64);
555 Rets.push_back(wasm::ValType::F64);
556 Params.push_back(wasm::ValType::F64);
559 Rets.push_back(wasm::ValType::F64);
563 Rets.push_back(wasm::ValType::F64);
572 Params.push_back(wasm::ValType::F64);
584 Params.push_back(wasm::ValType::F64);
606 Rets.push_back(wasm::ValType::F64);
    [all...]
WebAssemblyMCInstLower.cpp 218 return wasm::ValType::F64;
WebAssemblyAsmPrinter.cpp 63 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
119 case wasm::ValType::F64:
  /src/external/apache2/llvm/dist/llvm/include/llvm/Demangle/
RustDemangle.h 47 F64,
  /src/external/apache2/llvm/dist/llvm/lib/Demangle/
RustDemangle.cpp 255 // | "d" // f64
285 Type = BasicType::F64;
390 case BasicType::F64:
391 print("f64");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULibCalls.cpp 223 // FuncTbl works for both f32 and f64 functions with 1 input argument
533 getArgType(FInfo) == AMDGPULibFunc::F64 || !HasNative(FInfo.getId()) ||
698 getArgType(FInfo) == AMDGPULibFunc::F64)
755 } else { // F64
1102 // convert int(32) to fp(f32 or f64)
1236 if (getArgType(FInfo) == AMDGPULibFunc::F64 || !HasNative(FInfo.getId()))
1424 opr0 = (getArgType(FInfo) == AMDGPULibFunc::F64)
1430 opr1 = (getArgType(FInfo) == AMDGPULibFunc::F64)
1436 opr2 = (getArgType(FInfo) == AMDGPULibFunc::F64)
AMDGPULibFunc.h 272 F64 = FLOAT | B64,
AMDGPULibFunc.cpp 628 case 'd': res.ArgType = AMDGPULibFunc::F64; break;
735 case AMDGPULibFunc::F64: return "d";
884 case AMDGPULibFunc::F64: T = Type::getDoubleTy(C); break;
  /src/external/apache2/llvm/dist/llvm/include/llvm/BinaryFormat/
Wasm.h 396 F64 = WASM_TYPE_F64,
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
AMDGPUMetadata.h 107 F64 = 11,
  /src/external/apache2/llvm/dist/llvm/lib/Support/
AMDGPUMetadata.cpp 87 YIO.enumCase(EN, "F64", ValueType::F64);
  /src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/
WasmYAML.cpp 585 ECase(F64);
  /src/external/gpl3/gcc/dist/gcc/
builtins.def 87 DEF_GCC_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \
128 DEF_FLOATN_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \
builtins.cc 1907 types, there are additional types that are considered with 'F32', 'F64',
1919 fcodef32 = BUILT_IN_##MATHFN##F32; fcodef64 = BUILT_IN_##MATHFN##F64 ; \
2145 case CFN_BUILT_IN_##MATHFN##F64: \
tree.h 312 case FN##F16: case FN##F32: case FN##F64: case FN##F128: \
  /src/external/gpl3/gcc.old/dist/gcc/
builtins.def 87 DEF_GCC_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \
129 DEF_FLOATN_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \
builtins.cc 1892 types, there are additional types that are considered with 'F32', 'F64',
1904 fcodef32 = BUILT_IN_##MATHFN##F32; fcodef64 = BUILT_IN_##MATHFN##F64 ; \
2117 case CFN_BUILT_IN_##MATHFN##F64: \
tree.h 232 case FN##F16: case FN##F32: case FN##F64: case FN##F128: \
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 168 if (ElemTy != MVT::f64)
228 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
743 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
747 setAllExpand(MVT::f64);
781 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
821 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
1007 // operations, f64 is legal for the few double-precision instructions which
1010 setOperationAction(ISD::FADD, MVT::f64, Expand);
1011 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1012 setOperationAction(ISD::FMUL, MVT::f64, Expand)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 199 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
202 for (auto VT : {MVT::f32, MVT::f64, MVT::f80}) {
248 // to allow f80 to use i16 and f64 to use i16 with sse1 only
251 // f32 and f64 cases are Legal with SSE1/SSE2, f80 case is not
254 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
268 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 setOperationAction(ISD::LRINT, MVT::f64, Custom);
289 setOperationAction(ISD::LLRINT, MVT::f64, Custom);
319 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
320 // Without SSE, i64->f64 goes through memory
    [all...]

Completed in 117 milliseconds