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  /src/external/gpl3/binutils/dist/gas/config/
rx-parse.h 118 FADD = 319, /* FADD */
287 #define FADD 319
rx-parse.y 161 %token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOD FTOI FTOU
676 | FADD { sub_op = 2; } float3_op
1387 OPC(FADD),
rx-parse.c 300 FADD = 319, /* FADD */
469 #define FADD 319
663 YYSYMBOL_FADD = 64, /* FADD */
1326 "EMULU", "FADD", "FCMP", "FDIV", "FMUL", "FREIT", "FSUB", "FSQRT",
4733 OPC(FADD),
  /src/external/gpl3/binutils.old/dist/gas/config/
rx-parse.h 118 FADD = 319, /* FADD */
287 #define FADD 319
rx-parse.y 161 %token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOD FTOI FTOU
676 | FADD { sub_op = 2; } float3_op
1387 OPC(FADD),
rx-parse.c 300 FADD = 319, /* FADD */
469 #define FADD 319
663 YYSYMBOL_FADD = 64, /* FADD */
1326 "EMULU", "FADD", "FCMP", "FDIV", "FMUL", "FREIT", "FSUB", "FSQRT",
4733 OPC(FADD),
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 371 FADD,
1206 /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7]
1207 /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3]
1208 /// RES = FADD PART_RDX2[0], PART_RDX2[1]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd
618 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
623 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
790 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
791 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
849 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
850 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/
851 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
852 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
940 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org
    [all...]
X86IntrinsicsInfo.h 416 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
417 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
  /src/sys/arch/m68k/m68k/
db_disasm.h 345 #define FADD ENCFT(1,0,0,0,1,0)
  /src/sys/arch/sparc/include/
instr.h 410 #define FADD 0x40
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 4619 case AtomicRMWInst::FAdd: NT = ISD::ATOMIC_LOAD_FADD; break;
4933 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4936 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4949 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4952 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4955 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4970 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4973 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4976 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4979 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8
    [all...]
LegalizeVectorOps.cpp 374 case ISD::FADD:
600 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
1322 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO));
1343 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
DAGCombiner.cpp 1681 case ISD::FADD: return visitFADD(N);
12817 /// Try to perform FMA combining on a given FADD node.
12861 // If we have two choices trying to fold (fadd (fmul u, v), (fmul x, y)),
12868 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
12874 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
12875 // Note: Commutes FADD operands.
12881 // fadd (fma A, B, (fmul C, D)), E --> fma A, B, (fma C, D, E)
12882 // fadd E, (fma A, B, (fmul C, D)) --> fma A, B, (fma C, D, E)
12907 // fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
12920 // fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x
    [all...]
SelectionDAGBuilder.h 690 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
SelectionDAGDumper.cpp 252 case ISD::FADD: return "fadd";
LegalizeDAG.cpp 2426 Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt);
2433 // Don't expand it if there isn't cheap fadd.
2435 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT))
2504 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
3231 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3235 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3820 SDValue Fadd = DAG.getNode(ISD::STRICT_FADD, dl, Node->getVTList(),
3824 Results.push_back(Fadd);
3825 Results.push_back(Fadd.getValue(1));
4127 case ISD::FADD
    [all...]
LegalizeFloatTypes.cpp 73 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
1192 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1723 // TODO: Are there other fast-math-flags to propagate to this FADD?
1732 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo);
2247 case ISD::FADD:
2612 case ISD::FADD:
  /src/sys/arch/sparc/fpu/
fpu.c 491 case FADD >> 2:
492 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp 319 // Expand to fneg + fadd.
464 setOperationAction(ISD::FADD, VT, Expand);
559 setTargetDAGCombine(ISD::FADD);
586 case ISD::FADD:
2134 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2213 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2266 return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
2291 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2504 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
3670 case ISD::FADD:
    [all...]
AMDGPUTargetTransformInfo.cpp 622 // Check possible fuse {fadd|fsub}(a,fmul(b,c)) and return zero cost for
623 // fmul(b,c) supposing the fadd|fsub will get estimated cost for the whole
626 if (const auto *FAdd = dyn_cast<BinaryOperator>(*CxtI->user_begin())) {
627 const int OPC = TLI->InstructionOpcodeToISD(FAdd->getOpcode());
628 if (OPC == ISD::FADD || OPC == ISD::FSUB) {
638 (FAdd->hasAllowContract() && CxtI->hasAllowContract()))
643 case ISD::FADD:
SIISelLowering.cpp 681 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
713 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
729 setOperationAction(ISD::FADD, MVT::v2f32, Legal);
735 setOperationAction(ISD::FADD, VT, Custom);
801 setTargetDAGCombine(ISD::FADD);
4543 case ISD::FADD:
9350 case ISD::FADD:
9524 case ISD::FADD:
10163 case ISD::FADD:
10509 // fadd (fadd (a, a), b) -> mad 2.0, a,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 504 setTargetDAGCombine(ISD::FADD);
521 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
2098 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign);
2129 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA,
4363 if (User->getOpcode() != ISD::FADD)
4734 case ISD::FADD:
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeARM_64.c 85 #define FADD 0x1e602800
1758 FAIL_IF(push_inst(compiler, (FADD ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2)));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 1066 case ISD::FADD:
1535 case RecurKind::FAdd:
1599 case ISD::FADD:

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