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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineAtomicRMW.cpp 28 case AtomicRMWInst::FAdd: // -0.0
66 case AtomicRMWInst::FAdd:
138 // optimizer to match easily. The choices of or w/0 and fadd w/-0.0 are
145 RMWI.getOperation() != AtomicRMWInst::FAdd) {
146 RMWI.setOperation(AtomicRMWInst::FAdd);
InstCombineAddSub.cpp 9 // This file implements the visit functions for add, fadd, sub, and fsub.
175 /// FAddCombine is the class for optimizing an unsafe fadd/fsub along
182 Value *simplify(Instruction *FAdd);
355 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
435 assert((I->getOpcode() == Instruction::FAdd ||
614 // Note that at most three instructions are involved in Fadd-InstCombine: the
624 // Iterate the addends, creating fadd/fsub using adjacent two addends.
734 // <2/-2, V> "fadd V, V" coefficient is -2
1478 /// Factor a common operand out of fadd/fsub of fmul/fdiv.
1481 assert((I.getOpcode() == Instruction::FAdd ||
    [all...]
InstCombineCalls.cpp 1369 // Canonicalize fast fmuladd to the separate fmul + fadd.
1384 auto *FAdd = BinaryOperator::CreateFAdd(V, II->getArgOperand(2));
1385 FAdd->copyFastMathFlags(II);
1386 return FAdd;
1415 auto *FAdd = BinaryOperator::CreateFAdd(V, II->getArgOperand(2));
1416 FAdd->copyFastMathFlags(II);
1417 return FAdd;
InstCombineVectorOps.cpp 1494 case Instruction::FAdd:
1559 case Instruction::FAdd:
1649 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
IVDescriptors.cpp 78 case RecurKind::FAdd:
196 // Currently only FAdd is supported
197 if (Kind != RecurKind::FAdd)
201 Exit->getOpcode() == Instruction::FAdd && Exit == ExactFPMathInst;
357 if (IsASelect && (Kind == RecurKind::FAdd || Kind == RecurKind::FMul) &&
555 /// %add = fadd %0, %sum.1
586 return InstDesc(Kind == RecurKind::FAdd, SI);
618 case Instruction::FAdd:
619 return InstDesc(Kind == RecurKind::FAdd, I,
622 if (Kind == RecurKind::FAdd || Kind == RecurKind::FMul
    [all...]
CFLGraph.h 569 case Instruction::FAdd:
ObjCARCInstKind.cpp 253 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXTargetTransformInfo.cpp 259 return {Instruction::FAdd, FTZ_Any};
261 return {Instruction::FAdd, FTZ_MustBeOff};
263 return {Instruction::FAdd, FTZ_MustBeOn};
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsOs16.cpp 81 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
Float2Int.cpp 41 // integer domain inputs, produce an integer output; fadd, for example.
114 case Instruction::FAdd: return Instruction::Add;
214 case Instruction::FAdd:
263 case Instruction::FAdd:
493 case Instruction::FAdd:
LowerAtomic.cpp 90 case AtomicRMWInst::FAdd:
SpeculativeExecution.cpp 240 case Instruction::FAdd:
Reassociate.cpp 336 if (Opcode == Instruction::Add || Opcode == Instruction::FAdd) {
833 isReassociableOp(V, Instruction::Add, Instruction::FAdd)) {
1031 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) ||
1035 if (isReassociableOp(V1, Instruction::Add, Instruction::FAdd) ||
1040 (isReassociableOp(VB, Instruction::Add, Instruction::FAdd) ||
1974 case Instruction::FAdd:
2088 /// Given an fadd/fsub with an operand that is a one-use instruction
2089 /// (the fadd/fsub), try to change negative floating-point constants into
2094 assert((I->getOpcode() == Instruction::FAdd ||
2095 I->getOpcode() == Instruction::FSub) && "Expected fadd/fsub")
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVTargetTransformInfo.h 157 case RecurKind::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/FuzzMutate/
Operations.cpp 46 Ops.push_back(binOpDescriptor(1, Instruction::FAdd));
111 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
IVDescriptors.h 48 FAdd, ///< Sum of floats.
259 // Currently only a non-reassociative FAdd can be considered in-order,
260 // if it is also the only FAdd in the PHI's use chain.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
ExpandReductions.cpp 34 return Instruction::FAdd;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MVELaneInterleavingPass.cpp 235 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstCombineIntrinsic.cpp 884 auto *FAdd = IC.Builder.CreateFAddFMF(Zero, Op2, &II);
885 FAdd->takeName(&II);
886 return IC.replaceInstUsesWith(II, FAdd);
AMDGPUTargetTransformInfo.cpp 622 // Check possible fuse {fadd|fsub}(a,fmul(b,c)) and return zero cost for
623 // fmul(b,c) supposing the fadd|fsub will get estimated cost for the whole
626 if (const auto *FAdd = dyn_cast<BinaryOperator>(*CxtI->user_begin())) {
627 const int OPC = TLI->InstructionOpcodeToISD(FAdd->getOpcode());
628 if (OPC == ISD::FADD || OPC == ISD::FSUB) {
638 (FAdd->hasAllowContract() && CxtI->hasAllowContract()))
643 case ISD::FADD:
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
Instruction.h 545 case Add: case FAdd:
Operator.h 387 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/
ExecutionEngine.cpp 773 case Instruction::FAdd:
808 case Instruction::FAdd:
823 case Instruction::FAdd:
842 case Instruction::FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/IR/
Instruction.cpp 338 case FAdd: return "fadd";
721 case FAdd:
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZTargetTransformInfo.cpp 438 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
513 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
1039 // case Instruction::FAdd:

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