| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 466 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
469 /// FCOPYSIGN(f32, f64) is allowed.
470 FCOPYSIGN,
|
| BasicTTIImpl.h | 1568 ISDs.push_back(ISD::FCOPYSIGN);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 77 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
838 case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break;
1085 return DAG.getNode(ISD::FCOPYSIGN, dl, LVT, LHS, RHS);
1196 case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1768 case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1867 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
2081 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
2114 // Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by
2223 case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
2384 // FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the resul
[all...] |
| SelectionDAGDumper.cpp | 265 case ISD::FCOPYSIGN: return "fcopysign";
|
| LegalizeDAG.cpp | 1564 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1628 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1630 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1632 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
3120 case ISD::FCOPYSIGN:
4711 case ISD::FCOPYSIGN:
4717 // fcopysign doesn't change anything but the sign bit, so
4718 // (fp_round (fcopysign (fpext a), b))
4722 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
[all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::FCOPYSIGN:
925 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
1356 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
1357 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
2165 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
3074 case ISD::FCOPYSIGN:
3725 // If this is an FCOPYSIGN with same input types, we can treat it as a
4538 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
|
| LegalizeVectorOps.cpp | 414 case ISD::FCOPYSIGN:
|
| DAGCombiner.cpp | 1689 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
12553 // fold (bitconvert (fcopysign cst, x)) ->
12559 // fold (bitcast (fcopysign cst, x)) ->
12564 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
14255 // FCOPYSIGN on SSE registers yet.
14276 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
14296 N0.getOpcode() == ISD::FCOPYSIGN)
14297 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0.getOperand(0), N1);
14304 if (N1.getOpcode() == ISD::FCOPYSIGN)
14305 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1.getOperand(1))
[all...] |
| SelectionDAG.cpp | 4311 case ISD::FCOPYSIGN: {
5407 case ISD::FCOPYSIGN:
5611 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
5615 "Invalid FCOPYSIGN!");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 547 // 'Expand' implements FCOPYSIGN without calling an external library.
548 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
549 setOperationAction(ISD::FCOPYSIGN, MVT::v2f16, Expand);
550 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
551 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
2142 RoundedA = DAG.getNode(ISD::FCOPYSIGN, SL, VT, RoundedA, A);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1645 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 206 // fcopysign can be done in a single instruction with BFI.
207 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
208 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
| AMDGPUISelLowering.cpp | 487 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
2209 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2257 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);
|
| SIISelLowering.cpp | 417 // fcopysign can be done in a single instruction with BFI.
418 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
419 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
9396 // fcopysign, select and others may be lowered to 32-bit bit operations
9559 case ISD::FCOPYSIGN:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 356 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
357 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1220 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
|
| MipsSEISelLowering.cpp | 141 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 808 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 574 setOperationAction(ISD::FCOPYSIGN, VT, Legal);
765 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
817 setTargetDAGCombine(ISD::FCOPYSIGN);
2404 case ISD::FCOPYSIGN:
5846 case ISD::FCOPYSIGN: {
5867 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N->getOperand(0),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 419 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
567 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
652 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
662 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
959 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
1373 // But we do support custom-lowering for FCOPYSIGN.
1374 setOperationAction(ISD::FCOPYSIGN, VT, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 400 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
401 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
403 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
404 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1077 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1078 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1215 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 241 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 210 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 573 // Use ANDPD and ORPD to simulate FCOPYSIGN.
574 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
607 // Use ANDPS and ORPS to simulate FCOPYSIGN.
609 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
610 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
631 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
683 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
747 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
807 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
890 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 833 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
1016 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1394 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1395 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1467 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
5728 // Implement fcopysign with a fabs and a conditional fneg.
9866 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1490 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1594 ISD::FPOW, ISD::FCOPYSIGN}) {
|
