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    Searched refs:FDI_RX_CTL (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/dev/pci/
igmareg.h 149 #define FDI_RX_CTL(i) (0xf000c+i*0x1000)
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_ddi.c 1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1141 POSTING_READ(FDI_RX_CTL(PIPE_A));
1146 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1165 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1180 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1181 POSTING_READ(FDI_RX_CTL(PIPE_A));
1211 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1212 POSTING_READ(FDI_RX_CTL(PIPE_A));
1219 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
3898 val = I915_READ(FDI_RX_CTL(PIPE_A))
    [all...]
intel_display.c 1170 val = I915_READ(FDI_RX_CTL(pipe));
1202 val = I915_READ(FDI_RX_CTL(pipe));
4997 reg = FDI_RX_CTL(pipe);
5050 reg = FDI_RX_CTL(pipe);
5085 reg = FDI_RX_CTL(pipe);
5155 reg = FDI_RX_CTL(pipe);
5208 reg = FDI_RX_CTL(pipe);
5285 reg = FDI_RX_CTL(pipe);
5306 reg = FDI_RX_CTL(pipe);
5341 reg = FDI_RX_CTL(pipe)
    [all...]
intel_crt.c 1082 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
handlers.c 591 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; local
598 fdi_rx_ctl = FDI_RX_CTL(pipe);
622 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
645 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
2243 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2244 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2245 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 8581 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)

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