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    Searched refs:FIOp (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.cpp 204 int SPAdj, unsigned FIOp,
219 int FI = MI.getOperand(FIOp).getIndex();
224 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
230 MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
231 MI.RemoveOperand(FIOp+1);
342 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, false);
343 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 738 MachineOperand *FIOp =
745 assert(FIOp && FIOp->isFI() && "frame index must be address operand");
752 FIOp->ChangeToRegister(BaseReg, false);
765 FIOp->ChangeToRegister(BaseReg, false);
1510 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
1628 FIOp.ChangeToRegister(FrameReg, false);
1660 FIOp.ChangeToImmediate(Offset);
1661 if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp))
1667 FIOp.ChangeToRegister(AMDGPU::M0, false)
    [all...]
SILowerSGPRSpills.cpp 356 unsigned FIOp = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
358 int FI = MI.getOperand(FIOp).getIndex();
369 TRI->eliminateFrameIndex(MI, 0, FIOp, RS.get());
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetLowering.h 3425 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3428 virtual void computeKnownBitsForFrameIndex(int FIOp,

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