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    Searched refs:FMOV (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/arch/sparc/include/
instr.h 406 #define FMOV 0x00
  /src/sys/arch/sparc/fpu/
fpu.c 460 case FMOV >> 2: /* these should all be pretty obvious */
461 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n"));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.h 163 FMOV,
AArch64ISelLowering.cpp 1895 MAKE_CASE(AArch64ISD::FMOV)
6808 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
7628 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit, 32-bit cases, and
7638 // TODO: fmov h0, w0 is also legal, however on't have an isel pattern to
7639 // generate that fmov.
7641 // If we can not materialize in immediate field for fmov, check if the
7645 // The cost is actually exactly the same for mov+fmov vs. adrp+ldr;
7646 // however the mov+fmov sequence is always better because of the reduced
7648 // movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
9696 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits))
    [all...]
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeARM_64.c 90 #define FMOV 0x1e604000
1708 FAIL_IF(push_inst(compiler, (FMOV ^ inv_bits) | VD(dst_r) | VN(src)));

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