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    Searched refs:FMT_CONTROL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_opp.h 48 SRI(FMT_CONTROL, FMT, id), \
113 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
122 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
123 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
124 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
128 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
129 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
130 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
134 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
135 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),
    [all...]
amdgpu_dce_opp.c 195 REG_UPDATE_2(FMT_CONTROL,
199 REG_UPDATE_2(FMT_CONTROL,
205 REG_UPDATE_2(FMT_CONTROL,
393 REG_UPDATE_3(FMT_CONTROL,
398 REG_UPDATE_2(FMT_CONTROL,
403 REG_UPDATE_2(FMT_CONTROL,
408 REG_UPDATE_3(FMT_CONTROL,
448 REG_UPDATE(FMT_CONTROL,
501 REG_UPDATE(FMT_CONTROL,
505 REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 84 REG_UPDATE_2(FMT_CONTROL,
88 REG_UPDATE_2(FMT_CONTROL,
95 REG_UPDATE_2(FMT_CONTROL,
173 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
176 REG_UPDATE_3(FMT_CONTROL,
182 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
331 REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
dcn10_opp.h 40 SRI(FMT_CONTROL, FMT, id), \
57 uint32_t FMT_CONTROL; \
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 986 #define FMT_CONTROL 0x6fb8
evergreend.h 1375 #define FMT_CONTROL 0x6fb8
r600d.h 1244 #define FMT_CONTROL 0x6700

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