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    Searched refs:FORMAT_CONTROL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_dpp.c 118 REG_SET_2(FORMAT_CONTROL, 0,
123 //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14
124 //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled
125 //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled
126 //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled
127 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
128 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
129 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
130 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
224 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_ipp.h 37 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
170 uint32_t FORMAT_CONTROL;
amdgpu_dcn10_dpp.c 323 REG_SET_3(FORMAT_CONTROL, 0,
329 REG_SET_3(FORMAT_CONTROL, 0,
400 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
dcn10_dpp.h 119 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
1332 uint32_t FORMAT_CONTROL; \
amdgpu_dcn10_dpp_cm.c 719 REG_SET_3(FORMAT_CONTROL, 0,

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