| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetOptionsImpl.cpp | 33 StringRef FP = F.getFnAttribute("frame-pointer").getValueAsString();
34 if (FP == "all")
36 if (FP == "non-leaf")
38 if (FP == "none")
|
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| a2.s | 26 FP = P0;
28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 )
[all...] |
| stk5.s | 7 FP = SP;
16 R5 = [ FP + 8 ];
18 R5 = [ FP + 12 ];
|
| a3.s | 108 FP = P1;
110 R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
111 R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
112 R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
113 R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
114 R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
115 R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
116 R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
117 R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
118 R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 )
[all...] |
| c_ldstiifp_st_dreg.s | 32 loadsym fp, DATA_ADDR_1, 0xC8;
35 [ FP + -4 ] = R0;
36 [ FP + -8 ] = R1;
37 [ FP + -12 ] = R2;
38 [ FP + -16 ] = R3;
39 [ FP + -20 ] = R4;
40 [ FP + -24 ] = R5;
41 [ FP + -28 ] = R6;
42 [ FP + -32 ] = R7;
43 R6 = [ FP + -4 ]
[all...] |
| c_regmv_pr_pr.s | 13 imm32 fp, 0x200e100f;
19 imm32 fp, 0x200e100f;
24 FP = P1;
29 CHECKREG fp, 0x20021003;
35 imm32 fp, 0x200e100f;
40 FP = P2;
45 CHECKREG fp, 0x20041005;
51 imm32 fp, 0x200e100f;
56 FP = P4;
61 CHECKREG fp, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xAF357045;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 1 );
50 CHECKREG fp, 0x27D27AD4;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xC28BAC23;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 2 );
50 CHECKREG fp, 0xF92C5B7C;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 19 imm32 fp, 0x206e109f;
26 FP = ( FP + P1 ) << 1;
33 CHECKREG fp, 0x49FD416E;
41 imm32 fp, 0x200e10bf;
48 FP = ( FP + P2 ) << 2;
55 CHECKREG fp, 0x40BA439C;
63 imm32 fp, 0x200e100f;
70 FP = ( FP + P3 ) << 2
[all...] |
| c_compi2opp_pr_eq_i7_n.s | 15 FP = -7;
23 CHECKREG fp, -7;
32 FP = -15;
40 CHECKREG fp, -15;
49 FP = -23;
57 CHECKREG fp, -23;
66 FP = -31;
74 CHECKREG fp, -31;
83 FP = -39;
91 CHECKREG fp, -39
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| a2.s | 26 FP = P0;
28 R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
29 R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
30 R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
31 R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
32 R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
33 R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
34 R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
35 R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
36 R0 = [ FP + 32 ]; DBGA ( R0.L , 58 )
[all...] |
| stk5.s | 7 FP = SP;
16 R5 = [ FP + 8 ];
18 R5 = [ FP + 12 ];
|
| a3.s | 108 FP = P1;
110 R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
111 R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
112 R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
113 R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
114 R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
115 R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
116 R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
117 R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
118 R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 )
[all...] |
| c_ldstiifp_st_dreg.s | 32 loadsym fp, DATA_ADDR_1, 0xC8;
35 [ FP + -4 ] = R0;
36 [ FP + -8 ] = R1;
37 [ FP + -12 ] = R2;
38 [ FP + -16 ] = R3;
39 [ FP + -20 ] = R4;
40 [ FP + -24 ] = R5;
41 [ FP + -28 ] = R6;
42 [ FP + -32 ] = R7;
43 R6 = [ FP + -4 ]
[all...] |
| c_regmv_pr_pr.s | 13 imm32 fp, 0x200e100f;
19 imm32 fp, 0x200e100f;
24 FP = P1;
29 CHECKREG fp, 0x20021003;
35 imm32 fp, 0x200e100f;
40 FP = P2;
45 CHECKREG fp, 0x20041005;
51 imm32 fp, 0x200e100f;
56 FP = P4;
61 CHECKREG fp, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xAF357045;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 1 );
50 CHECKREG fp, 0x27D27AD4;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 14 imm32 fp, 0x12341678;
21 FP = P1 + FP;
28 CHECKREG fp, 0xC28BAC23;
36 imm32 fp, 0x12345628;
43 FP = P2 + ( FP << 2 );
50 CHECKREG fp, 0xF92C5B7C;
58 imm32 fp, 0x12345673;
65 FP = P3 + ( FP << 2 )
[all...] |
| c_ptr2op_pr_shadd_1_2.s | 19 imm32 fp, 0x206e109f;
26 FP = ( FP + P1 ) << 1;
33 CHECKREG fp, 0x49FD416E;
41 imm32 fp, 0x200e10bf;
48 FP = ( FP + P2 ) << 2;
55 CHECKREG fp, 0x40BA439C;
63 imm32 fp, 0x200e100f;
70 FP = ( FP + P3 ) << 2
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonEarlyIfConv.cpp | 136 : FP(P), TRI(T) {}
138 const FlowPattern &FP;
145 OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
147 << ", TrueB:" << PrintMB(P.FP.TrueB)
148 << ", FalseB:" << PrintMB(P.FP.FalseB)
149 << ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
178 FlowPattern &FP);
186 bool isValid(const FlowPattern &FP) const;
189 const FlowPattern &FP) const
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| aarch64-simd-builtins.def | 59 BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, FP)
60 BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP)
440 BUILTIN_VHSDF (BINOP, fcadd90, 0, FP)
441 BUILTIN_VHSDF (BINOP, fcadd270, 0, FP)
444 BUILTIN_VHSDF (TERNOP, fcmla0, 0, FP)
445 BUILTIN_VHSDF (TERNOP, fcmla90, 0, FP)
446 BUILTIN_VHSDF (TERNOP, fcmla180, 0, FP)
447 BUILTIN_VHSDF (TERNOP, fcmla270, 0, FP)
448 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, FP)
449 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, FP)
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| aarch64-simd-builtins.def | 52 BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0, FP)
53 BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP)
439 BUILTIN_VHSDF (BINOP, fcadd90, 0, FP)
440 BUILTIN_VHSDF (BINOP, fcadd270, 0, FP)
443 BUILTIN_VHSDF (TERNOP, fcmla0, 0, FP)
444 BUILTIN_VHSDF (TERNOP, fcmla90, 0, FP)
445 BUILTIN_VHSDF (TERNOP, fcmla180, 0, FP)
446 BUILTIN_VHSDF (TERNOP, fcmla270, 0, FP)
447 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane0, 0, FP)
448 BUILTIN_VHSDF (QUADOP_LANE_PAIR, fcmla_lane90, 0, FP)
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| alpha-opc.c | 215 /* The plain fp register fields. */
349 #define FP(oo,fff) FP_(oo,fff), FP_MASK
666 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
667 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
668 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
669 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
670 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
671 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
672 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
673 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| alpha-opc.c | 215 /* The plain fp register fields. */
349 #define FP(oo,fff) FP_(oo,fff), FP_MASK
666 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
667 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
668 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
669 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
670 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
671 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
672 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
673 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| alpha-opc.c | 215 /* The plain fp register fields. */
349 #define FP(oo,fff) FP_(oo,fff), FP_MASK
666 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
667 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
668 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
669 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
670 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
671 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
672 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
673 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| alpha-opc.c | 215 /* The plain fp register fields. */
349 #define FP(oo,fff) FP_(oo,fff), FP_MASK
666 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
667 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
668 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
669 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
670 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
671 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
672 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
673 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }
[all...] |
