| /src/external/gpl3/gdb/dist/sim/ppc/ |
| idecode_expression.h | 259 CR_SET(1, EXTRACTED32(FPSCR, fpscr_fx_bit, fpscr_ox_bit)); \
315 /* some FPSCR update macros. */
319 fpscreg old_fpscr ATTRIBUTE_UNUSED = FPSCR
323 if ((FPSCR & fpscr_vx_bits)) \
324 FPSCR |= fpscr_vx; \
326 FPSCR &= ~fpscr_vx; \
328 if (((FPSCR & fpscr_vx) && (FPSCR & fpscr_ve)) \
329 || ((FPSCR & fpscr_ox) && (FPSCR & fpscr_oe))
[all...] |
| powerpc.igen | 185 #define PPC_FPSCR_REG (PPC_CR_REG + 8) /* start of fpscr register */
199 uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
231 uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
324 TRACE(trace_model, ("Register fpscr is now available.\n"));
390 TRACE(trace_model, ("Waiting for register fpscr.\n"));
1086 if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) {
1091 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) {
1096 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) {
1168 FPSCR_SET_XX(FPSCR & fpscr_fi);
1226 FPSCR_SET_XX(FPSCR & fpscr_fi)
[all...] |
| registers.h | 267 fpscreg fpscr; member in struct:_registers
345 #define FPSCR cpu_registers(processor)->fpscr
|
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| idecode_expression.h | 259 CR_SET(1, EXTRACTED32(FPSCR, fpscr_fx_bit, fpscr_ox_bit)); \
315 /* some FPSCR update macros. */
319 fpscreg old_fpscr ATTRIBUTE_UNUSED = FPSCR
323 if ((FPSCR & fpscr_vx_bits)) \
324 FPSCR |= fpscr_vx; \
326 FPSCR &= ~fpscr_vx; \
328 if (((FPSCR & fpscr_vx) && (FPSCR & fpscr_ve)) \
329 || ((FPSCR & fpscr_ox) && (FPSCR & fpscr_oe))
[all...] |
| powerpc.igen | 185 #define PPC_FPSCR_REG (PPC_CR_REG + 8) /* start of fpscr register */
199 uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
231 uint32_t cr_fpscr_busy; /* CR/FPSCR registers that are busy */
324 TRACE(trace_model, ("Register fpscr is now available.\n"));
390 TRACE(trace_model, ("Waiting for register fpscr.\n"));
1086 if ((FPSCR & fpscr_rn) == fpscr_rn_round_to_nearest) {
1091 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_pos_infinity) {
1096 if ((FPSCR & fpscr_rn) == fpscr_rn_round_towards_neg_infinity) {
1168 FPSCR_SET_XX(FPSCR & fpscr_fi);
1226 FPSCR_SET_XX(FPSCR & fpscr_fi)
[all...] |
| registers.h | 267 fpscreg fpscr; member in struct:_registers
345 #define FPSCR cpu_registers(processor)->fpscr
|
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| armsupp.c | 1424 state->FPSCR &= 0x0FFFFFFF;
1426 state->FPSCR |= NBIT;
1428 state->FPSCR |= CBIT;
1430 state->FPSCR |= ZBIT;
1432 state->FPSCR |= VBIT;
1437 state->FPSCR & NBIT ? 'N' : '-',
1438 state->FPSCR & ZBIT ? 'Z' : '-',
1439 state->FPSCR & CBIT ? 'C' : '-',
1440 state->FPSCR & VBIT ? 'V' : '-');
1464 state->FPSCR &= 0x0FFFFFFF
[all...] |
| armdefs.h | 164 ARMword FPSCR; /* Floating Point Status Register. */
|
| armemu.c | 4676 ARMul_SetCPSR (state, (state->FPSCR & 0xF0000000)
4688 state->Reg[DESTReg] = state->FPSCR;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 240 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 197 markSuperRegs(Reserved, ARM::FPSCR);
|
| ARMISelLowering.cpp | 6097 // The rounding mode is in bits 23:22 of the FPSCR.
6099 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
6106 SDValue FPSCR =
6108 Chain = FPSCR.getValue(1);
6109 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
6124 // The rounding mode is in bits 23:22 of the FPSCR.
6134 // Calculate new value of FPSCR[23:22].
6142 // Get current value of FPSCR.
6145 SDValue FPSCR =
6147 Chain = FPSCR.getValue(1)
[all...] |
| ARMExpandPseudoInsts.cpp | 1001 // S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
1185 // Clear FPSCR bits 0-4, 7, 28-31
1260 // Store an available register for FPSCR clearing
1316 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
1363 // restore FPSCR from stack and clear bits 0-4, 7, 28-31
1410 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
|
| /src/external/gpl3/gdb.old/dist/gdb/ |
| rs6000-aix-nat.c | 238 return FPSCR;
|
| /src/external/gpl3/gdb/dist/gdb/ |
| rs6000-aix-nat.c | 238 return FPSCR;
|
| /src/external/gpl3/gcc/dist/gcc/config/arm/ |
| arm.h | 344 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All
1160 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */
1164 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can
1396 DEF_FP_SYSREG (FPSCR) \
|
| /src/external/gpl3/gcc.old/dist/gcc/config/arm/ |
| arm.h | 338 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All
1142 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */
1146 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can
1372 DEF_FP_SYSREG (FPSCR) \
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 6409 {"FPSCR", 0x1, 0x0},
9929 first_error (_("operand 1 must be FPSCR"));
9973 case 1: /* fpscr. */
23726 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23727 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 6408 {"FPSCR", 0x1, 0x0},
9932 first_error (_("operand 1 must be FPSCR"));
9976 case 1: /* fpscr. */
23729 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23730 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
|
