| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 435 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
793 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
796 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
802 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
803 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
804 FP_ROUND,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 813 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 },
814 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 },
815 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 },
818 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 },
819 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 },
820 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 },
823 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 },
824 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 },
825 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 },
|
| AArch64ISelLowering.cpp | 467 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
468 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
469 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
987 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
1243 setOperationAction(ISD::FP_ROUND, VT, Custom);
1276 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom);
1282 setOperationAction(ISD::FP_ROUND, VT, Expand);
3383 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
3410 ISD::FP_ROUND, dl, MVT::f16,
4539 case ISD::FP_ROUND
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 512 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1},
513 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3},
552 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 &&
558 {ISD::FP_ROUND, MVT::v2f64, 2},
746 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) {
|
| ARMISelDAGToDAG.cpp | 3073 if (Val1.getOpcode() == ISD::FP_ROUND || Val2.getOpcode() == ISD::FP_ROUND)
|
| ARMISelLowering.cpp | 916 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
1040 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1052 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
7264 // BUILDVECTOR(FP_ROUND(EXTRACT_ELT(X, 0),
7265 // FP_ROUND(EXTRACT_ELT(Y, 0),
7266 // FP_ROUND(EXTRACT_ELT(X, 1),
7267 // FP_ROUND(EXTRACT_ELT(Y, 1), ...)
7283 if (BV.getOperand(0).getOpcode() != ISD::FP_ROUND ||
7287 if (BV.getOperand(1).getOpcode() != ISD::FP_ROUND ||
7299 return Trunc.getOpcode() == ISD::FP_ROUND &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 104 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
549 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
815 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
817 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
864 // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
865 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 ||
875 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
1044 // Do an FP_ROUND followed by a non-truncating store.
1045 Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1770 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break
[all...] |
| LegalizeVectorOps.cpp | 432 case ISD::FP_ROUND:
589 case ISD::FP_ROUND:
628 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl));
|
| LegalizeDAG.cpp | 2838 // We might as well mutate to FP_ROUND when FP_ROUND operation is legal
2844 // We fall back to use stack operation when the FP_ROUND operation
2854 case ISD::FP_ROUND:
3208 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
4245 case ISD::FP_ROUND:
4247 // X = FP_ROUND(Y, TRUNC)
4249 // If TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND
4554 TruncOp = ISD::FP_ROUND;
4563 if (TruncOp != ISD::FP_ROUND)
[all...] |
| LegalizeVectorTypes.cpp | 55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
333 return DAG.getNode(ISD::FP_ROUND, DL,
640 case ISD::FP_ROUND:
814 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
987 case ISD::FP_ROUND:
1923 if (N->getOpcode() == ISD::FP_ROUND) {
2164 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
2874 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2928 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2929 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1))
[all...] |
| SelectionDAGDumper.cpp | 341 case ISD::FP_ROUND: return "fp_round";
|
| DAGCombiner.cpp | 1695 case ISD::FP_ROUND: return visitFP_ROUND(N);
10600 CastOpcode == ISD::FP_ROUND) &&
10626 if (CastOpcode == ISD::FP_ROUND) {
10627 // FP_ROUND (fptrunc) has an extra flag operand to pass along.
14113 } else if (N1.getOpcode() == ISD::FP_ROUND &&
14117 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
14240 /// copysign(x, fp_round(y)) -> copysign(x, y)
14244 N1.getOpcode() == ISD::FP_ROUND)) {
14308 // copysign(x, fp_round(y)) -> copysign(x, y)
14596 // fold (fp_round c1fp) -> c1f
[all...] |
| SelectionDAG.cpp | 1245 : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL));
4318 case ISD::FP_ROUND: {
4810 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
5413 if (N1CFP && Opcode == ISD::FP_ROUND) {
5653 case ISD::FP_ROUND:
5658 "Invalid FP_ROUND!");
|
| SelectionDAGBuilder.cpp | 287 // FP_ROUND's are always exact here.
290 ISD::FP_ROUND, DL, ValueVT, Val,
3412 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
6324 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
|
| TargetLowering.cpp | 6239 case ISD::FP_ROUND:
6242 return DAG.getNode(ISD::FP_ROUND, DL, VT, NegV, Op.getOperand(1));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1726 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1754 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1755 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
2321 // FP_ROUND on f64 and f32 are legal.
3058 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 2532 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
2572 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);
3820 case ISD::FP_ROUND: {
3824 // (fneg (fp_round (fneg x))) -> (fp_round x)
3825 return DAG.getNode(ISD::FP_ROUND, SL, VT,
3832 // (fneg (fp_round x)) -> (fp_round (fneg x))
3834 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));
|
| SIISelLowering.cpp | 204 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
206 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
208 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
210 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
547 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
4514 case ISD::FP_ROUND:
5093 DAG.getNode(ISD::FP_ROUND, DL, VT, Op,
5099 "Do not know how to custom lower FP_ROUND for non-f16 type");
8359 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
8789 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt
[all...] |
| R600ISelLowering.cpp | 249 setTargetDAGCombine(ISD::FP_ROUND);
1759 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1760 case ISD::FP_ROUND: {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 1172 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1173 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1221 // Expand the fp_round if the source type is fp128.
1223 setOperationAction(ISD::FP_ROUND, VT, Custom);
8560 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
8641 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
8938 (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
10841 case ISD::FP_ROUND:
13632 // If we are converting to 32-bit integers, we need to add an FP_ROUND.
13652 // For 32-bit values, we need to add an FP_ROUND node (if we made i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 981 case ISD::FP_ROUND:
995 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break;
1207 case ISD::FP_ROUND:
1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT;
1252 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
1338 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
|
| X86TargetTransformInfo.cpp | 1548 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
1828 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
1924 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 },
|
| X86ISelLowering.cpp | 760 // We need to custom handle any FP_ROUND with an f128 input, but
764 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
768 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
772 setOperationAction(ISD::FP_ROUND, MVT::f80, Custom);
1046 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
2053 setTargetDAGCombine(ISD::FP_ROUND);
3102 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
20573 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
21948 DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DAG.getIntPtrConstant(0, dl));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1787 case FPTrunc: return ISD::FP_ROUND;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 554 // RVV has native FP_ROUND & FP_EXTEND conversions where the element type
558 setOperationAction(ISD::FP_ROUND, VT, Custom);
771 setOperationAction(ISD::FP_ROUND, VT, Custom);
2138 case ISD::FP_ROUND: {
2139 // RVV can only do fp_round to types half the size as the source. We
2162 // For fixed-length vectors, lower the FP_ROUND to a custom "VL" version.
2225 // One narrowing int_to_fp, then an fp_round.
5852 // this optimized pattern. Avoid modifying cases where FP_ROUND and
5860 (In2.getOpcode() != ISD::FP_ROUND || In2.getConstantOperandVal(1) != 0))
|
