| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 375 FREM,
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| TargetLowering.h | 2470 case ISD::FREM:
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| /src/sys/arch/m68k/m68k/ |
| db_disasm.h | 366 #define FREM ENCFT(1,0,0,1,0,1)
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| db_disasm.c | 1456 case FREM:
1457 get_fpustdGEN(dbuf,ext,"frem");
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 697 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
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| SelectionDAGDumper.cpp | 263 case ISD::FREM: return "frem";
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| LegalizeFloatTypes.cpp | 111 case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
1247 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
2255 case ISD::FREM:
2620 case ISD::FREM:
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| LegalizeVectorOps.cpp | 378 case ISD::FREM:
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| FastISel.cpp | 1705 case Instruction::FRem:
1706 return selectBinaryOp(I, ISD::FREM);
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| LegalizeVectorTypes.cpp | 136 case ISD::FREM:
1033 case ISD::FREM:
3042 case ISD::FREM:
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| LegalizeDAG.cpp | 4115 case ISD::FREM:
4676 case ISD::FREM:
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| SelectionDAG.cpp | 4287 case ISD::FREM:
5404 case ISD::FREM:
5433 case ISD::FREM:
5604 case ISD::FREM:
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 315 setOperationAction(ISD::FREM, MVT::f16, Custom);
316 setOperationAction(ISD::FREM, MVT::f32, Custom);
317 setOperationAction(ISD::FREM, MVT::f64, Custom);
471 setOperationAction(ISD::FREM, VT, Expand);
634 case ISD::FREM:
1244 case ISD::FREM: return LowerFREM(Op, DAG);
2097 // (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
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| AMDGPUTargetTransformInfo.cpp | 657 case ISD::FREM:
658 // FIXME: frem should be handled separately. The fdiv in it is most of it,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1628 setOperationAction(ISD::FREM , MVT::f128, Expand);
1633 setOperationAction(ISD::FREM , MVT::f64, Expand);
1638 setOperationAction(ISD::FREM , MVT::f32, Expand);
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 1766 case FRem: return ISD::FREM;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1593 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1638 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 348 setOperationAction(ISD::FREM, VT, Expand);
404 setOperationAction(ISD::FREM, MVT::f32, Expand);
405 setOperationAction(ISD::FREM, MVT::f64, Expand);
406 setOperationAction(ISD::FREM, MVT::f80, Expand);
426 setOperationAction(ISD::FREM, MVT::f128, Expand);
573 setOperationAction(ISD::FREM, MVT::f16, Promote);
574 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
575 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
968 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
1403 setOperationAction(ISD::FREM, VT, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 447 setOperationAction(ISD::FREM, MVT::f32, Expand);
448 setOperationAction(ISD::FREM, MVT::f64, Expand);
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| MipsSEISelLowering.cpp | 136 setOperationAction(ISD::FREM, MVT::f16, Promote);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 218 /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
224 setOperationAction(ISD::FREM, VT, Expand);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 213 setOperationAction(ISD::FREM, VT, Expand);
364 setOperationAction(ISD::FREM, VT, Expand);
826 // FIXME: Code duplication: FDIV and FREM are expanded always, see
829 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
1015 setOperationAction(ISD::FREM, MVT::f64, Expand);
1390 setOperationAction(ISD::FREM, MVT::f64, Expand);
1391 setOperationAction(ISD::FREM, MVT::f32, Expand);
1466 setOperationAction(ISD::FREM, MVT::f16, Promote);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 293 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
368 setOperationAction(ISD::FREM , MVT::f64, Expand);
373 setOperationAction(ISD::FREM , MVT::f32, Expand);
792 setOperationAction(ISD::FREM, VT, Expand);
1132 setOperationAction(ISD::FREM, MVT::f128, Expand);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 556 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
569 // No FPOW or FREM in PTX.
|
