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    Searched refs:FReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
EarlyIfConversion.cpp 114 unsigned TReg, FReg;
115 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
119 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
519 PI.FReg = PI.PHI->getOperand(i).getReg();
522 assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");
526 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
563 Register FReg) {
564 if (TReg == FReg)
567 if (!TReg.isVirtual() || !FReg.isVirtual())
571 const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg);
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  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 590 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
594 FalseReg = FReg;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 8116 unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
8150 if (FReg != RISCV::NoRegister) {
8151 assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg");
8153 unsigned RegNo = FReg - RISCV::F0_F;
8157 return std::make_pair(FReg, &RISCV::FPR32RegClass);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 3095 const Register FReg = I.getOperand(3).getReg();
3106 if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB))
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 6602 unsigned FReg = State.AllocateReg(FPR);
6603 if (FReg)
6604 State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo));
6609 assert(FReg && "An FPR should be available when a GPR is reserved.");
6626 FReg ? CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT,

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