| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 646 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
653 FSHR,
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 386 case ISD::FSHR:
805 case ISD::FSHR:
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| SelectionDAGDumper.cpp | 251 case ISD::FSHR: return "fshr";
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| LegalizeIntegerTypes.cpp | 230 case ISD::FSHR:
1186 bool IsFSHR = Opcode == ISD::FSHR;
1198 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
2214 case ISD::FSHR:
3490 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3492 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
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| DAGCombiner.cpp | 1655 case ISD::FSHR: return visitFunnelShift(N);
6839 // (fshl x0, x1, y) or (fshr x0, x1, (sub 32, y))
6843 // (fshr x0, x1, y) or (fshl x0, x1, (sub 32, y))
6871 // -> (fshr x0, x1, y)
6875 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) {
6876 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
6880 // -> (fshr x0, x1, y)
6885 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) {
6886 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
6907 bool HasFSHR = hasOperation(ISD::FSHR, VT)
[all...] |
| LegalizeVectorTypes.cpp | 155 case ISD::FSHR:
1050 case ISD::FSHR:
3154 case ISD::FSHR:
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| LegalizeDAG.cpp | 1220 case ISD::FSHR:
3362 case ISD::FSHR:
|
| TargetLowering.cpp | 1679 case ISD::FSHR: {
1689 // For fshr, 0-shift returns the 2nd arg.
1698 // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
6480 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL;
6484 // fshl X, Y, Z -> fshr X, Y, -Z
6485 // fshr X, Y, Z -> fshl X, Y, -Z
6489 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z
6490 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z
6509 // fshr: X << (BW - C) | Y >>
[all...] |
| SelectionDAG.cpp | 3126 case ISD::FSHR:
3131 // For fshr, 0-shift returns the 2nd arg.
3139 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
|
| SelectionDAGBuilder.cpp | 6401 case Intrinsic::fshr: {
6412 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 37 /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD.
39 FSHR,
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| X86ISelLowering.cpp | 216 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
1756 setOperationAction(ISD::FSHR, VT, Custom);
19629 assert((Op.getOpcode() == ISD::FSHL || Op.getOpcode() == ISD::FSHR) &&
19637 bool IsFSHR = Op.getOpcode() == ISD::FSHR;
19678 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z & (bw-1))).
19705 unsigned FSHOp = (IsFSHR ? X86ISD::FSHR : X86ISD::FSHL);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 755 setOperationAction(ISD::FSHR, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1580 setOperationAction(ISD::FSHR, MVT::i32, Legal);
1581 setOperationAction(ISD::FSHR, MVT::i64, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 287 setOperationAction(ISD::FSHR, XLenVT, Custom);
292 setOperationAction(ISD::FSHR, MVT::i32, Custom);
2006 case ISD::FSHR: {
2012 // FSL/FSR take a log2(XLen)+1 bit shift amount but XLenVT FSHL/FSHR only
4893 case ISD::FSHR: {
4902 // FSLW/FSRW take a 6 bit shift amount but i32 FSHL/FSHR only use 5 bits.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 702 setOperationAction(ISD::FSHR, MVT::i64, Custom);
705 setOperationAction(ISD::FSHR, MVT::i32, Custom);
8819 // fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
10830 case ISD::FSHR: return LowerFunnelShift(Op, DAG);
10929 case ISD::FSHR:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 384 // The hardware supports 32-bit FSHR, but not FSHL.
385 setOperationAction(ISD::FSHR, MVT::i32, Legal);
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| SIISelLowering.cpp | 6704 return DAG.getNode(ISD::FSHR, DL, VT,
|
