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    Searched refs:FSINCOS (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 904 /// FSINCOS - Compute both fsin and fcos as a single operation.
905 FSINCOS,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 202 case ISD::FSINCOS: return "fsincos";
LegalizeDAG.cpp 2219 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
3157 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3159 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3163 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3973 case ISD::FSINCOS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1627 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1632 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1637 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 353 setOperationAction(ISD::FSINCOS, VT, Expand);
429 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
588 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
589 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
590 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
800 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
801 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
803 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
804 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
973 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 1593 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1642 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 437 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
438 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
MipsSEISelLowering.cpp 150 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 109 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1388 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1389 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1431 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1432 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1470 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
9937 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 583 setOperationAction(ISD::FSINCOS, VT, Expand);
615 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
621 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
636 setOperationAction(ISD::FSINCOS, VT, Expand);
702 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f128, LibCall);
804 setOperationAction(ISD::FSINCOS, VT, Expand);
1974 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1975 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 367 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
372 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 9564 case ISD::FSINCOS:
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 304 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 467 setOperationAction(ISD::FSINCOS, VT, Expand);

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