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    Searched refs:FSR (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/clang/lib/AST/
PrintfFormatString.cpp 418 const PrintfSpecifierResult &FSR = ParsePrintfSpecifier(H, I, E, argIndex,
423 if (FSR.shouldStop())
427 if (!FSR.hasValue())
430 if (!H.HandlePrintfSpecifier(FSR.getValue(), FSR.getStart(),
431 I - FSR.getStart()))
448 const PrintfSpecifierResult &FSR = ParsePrintfSpecifier(H, I, E, argIndex,
453 if (FSR.shouldStop())
457 if (!FSR.hasValue())
459 const analyze_printf::PrintfSpecifier &FS = FSR.getValue()
    [all...]
ScanfFormatString.cpp 549 const ScanfSpecifierResult &FSR = ParseScanfSpecifier(H, I, E, argIndex,
553 if (FSR.shouldStop())
557 if (!FSR.hasValue())
560 if (!H.HandleScanfSpecifier(FSR.getValue(), FSR.getStart(),
561 I - FSR.getStart())) {
  /src/lib/libc/arch/sparc64/gen/
modf.S 47 #include <machine/fsr.h>
74 * 4@[%fp + BIAS - 4] saved %fsr
75 * 4@[%fp + BIAS - 8] new %fsr with rounding set to `towards 0'
126 st %fsr, [%fp + BIAS - 4] ! %l5 = current FSR mode
134 ld [%fp + BIAS - 8], %fsr
140 * Restore %fsr, but leave exceptions accrued.
142 st %fsr, [%fp + BIAS - 4]
144 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
147 ld [%fp + BIAS - 4], %fsr ! restore %fsr, leaving accrued stuf
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonEarlyIfConv.cpp 204 unsigned TSR, unsigned FR, unsigned FSR);
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {
806 .addReg(FR, 0, FSR);
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
826 FR = RO.getReg(), FSR = RO.getSubReg();
835 FR = SR, FSR = SSR;
844 FP.PredR, TR, TSR, FR, FSR);
850 MuxSR = FSR;
  /src/lib/libc/arch/sparc/gen/
modf.S 47 #include <machine/fsr.h>
74 * 4@[%fp - 4] saved %fsr
75 * 4@[%fp - 8] new %fsr with rounding set to `towards 0'
131 st %fsr, [%fp - 4] ! %l5 = current FSR mode
139 ld [%fp - 8], %fsr
145 * Restore %fsr, but leave exceptions accrued.
147 st %fsr, [%fp - 4]
149 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
152 ld [%fp - 4], %fsr ! restore %fsr, leaving accrued stuf
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/
nds32-tdep.c 294 const int FSR = 38;
295 const int FDR = FSR + 32;
302 else if (num >= FSR && num < FSR + 32)
305 return num - FSR + tdep->fs0_regnum;
  /src/external/gpl3/gdb/dist/gdb/
nds32-tdep.c 294 const int FSR = 38;
295 const int FDR = FSR + 32;
302 else if (num >= FSR && num < FSR + 32)
305 return num - FSR + tdep->fs0_regnum;
  /src/sys/arch/arm/sociox/
sni_i2c.c 81 #define FSR 0x18 /* bus clock frequency */
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.h 66 FSR,
RISCVISelLowering.cpp 2012 // FSL/FSR take a log2(XLen)+1 bit shift amount but XLenVT FSHL/FSHR only
2017 unsigned Opc = Op.getOpcode() == ISD::FSHL ? RISCVISD::FSL : RISCVISD::FSR;
5595 case RISCVISD::FSR: {
7910 NODE_NAME_CASE(FSR)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 1019 case Sparc::FSR:
1020 Op = SparcOperand::CreateToken("%fsr", S);
1155 if (name.equals("fsr")) {
1156 RegNo = Sparc::FSR;

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