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    Searched refs:FalseReg (Results 1 - 18 of 18) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CmovConversion.cpp 715 Register FalseReg =
719 auto FRIt = FalseBBRegRewriteTable.find(FalseReg);
722 FalseReg = FRIt->second;
724 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
X86InstrInfo.h 352 Register FalseReg) const override;
X86InstrInfo.cpp 3309 Register FalseReg, int &CondCycles,
3323 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3347 Register FalseReg) const {
3355 .addReg(FalseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiInstrInfo.cpp 506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
531 // allocator ensure the FalseReg is allocated the same register as operand 0.
532 FalseReg.setImplicit();
533 NewMI.add(FalseReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.h 244 Register FalseReg) const override;
SystemZInstrInfo.cpp 536 Register FalseReg, int &CondCycles,
548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
572 Register FalseReg) const {
592 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
594 FalseReg = FReg;
605 .addReg(FalseReg).addReg(TrueReg)
SystemZISelLowering.cpp 7133 Register FalseReg = MI->getOperand(2).getReg();
7139 std::swap(TrueReg, FalseReg);
7144 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end())
7145 FalseReg = RegRewriteTable[FalseReg].second;
7150 .addReg(FalseReg).addMBB(FalseMBB);
7153 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
7238 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.h 304 Register TrueReg, Register FalseReg, int &CondCycles,
310 Register TrueReg, Register FalseReg) const override;
315 Register TrueReg, Register FalseReg) const;
SIInstrInfo.cpp 1049 Register FalseReg) const {
1062 .addReg(FalseReg)
1077 .addReg(FalseReg)
1091 .addReg(FalseReg)
1105 .addReg(FalseReg)
1121 .addReg(FalseReg)
1137 .addReg(FalseReg)
1155 .addReg(FalseReg)
2495 Register FalseReg, int &CondCycles,
2502 if (MRI.getRegClass(FalseReg) != RC
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 788 auto FalseReg = MIB.getReg(3);
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
795 .addUse(FalseReg)
ARMBaseInstrInfo.cpp 2343 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2345 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2373 // The tie makes the register allocator ensure the FalseReg is allocated the
2375 FalseReg.setImplicit();
2376 NewMI.add(FalseReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.h 219 Register FalseReg) const override;
AArch64InstrInfo.cpp 614 Register FalseReg, int &CondCycles,
620 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
642 else if (canFoldIntoCSel(MRI, FalseReg))
664 Register TrueReg, Register FalseReg) const {
770 // FalseReg, so we need to invert the condition.
772 TrueReg = FalseReg;
774 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
778 FalseReg = NewVReg;
787 MRI.constrainRegClass(FalseReg, RC);
792 .addReg(FalseReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 920 unsigned FalseReg = getRegForValue(Select->getFalseValue());
921 if (FalseReg == 0)
925 std::swap(TrueReg, FalseReg);
964 .addReg(FalseReg)
WebAssemblyISelLowering.cpp 409 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
414 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
447 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
451 .addReg(FalseReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1534 Register FalseReg, int &CondCycles,
1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1573 Register FalseReg) const {
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1581 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
1632 Register FirstReg = SwapOps ? FalseReg : TrueReg,
1633 SecondReg = SwapOps ? TrueReg : FalseReg;
3108 unsigned TrueReg, unsigned FalseReg,
3115 return Imm1 < Imm2 ? TrueReg : FalseReg;
3117 return Imm1 > Imm2 ? TrueReg : FalseReg;
    [all...]
PPCInstrInfo.h 429 Register FalseReg) const override;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetInstrInfo.h 844 /// instruction that chooses between TrueReg and FalseReg based on the
848 /// FalseReg, and Cond to the destination register. In most cases, a select
857 /// @param FalseReg Virtual register to select when Cond is false.
860 /// @param FalseCycles Latency from FalseReg to select output.
863 Register TrueReg, Register FalseReg,
870 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
883 /// @param FalseReg Virtual register to copy when Cons is false.
887 Register TrueReg, Register FalseReg) const {

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