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    Searched refs:FeatureBits (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCSubtargetInfo.cpp 210 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
221 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
241 FeatureBits.flip(FB);
242 return FeatureBits;
246 FeatureBits ^= FB;
247 return FeatureBits;
252 SetImpliedBits(FeatureBits, FB, ProcFeatures);
253 return FeatureBits;
260 FeatureBits.reset(I);
261 ClearImpliedBits(FeatureBits, I, ProcFeatures)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVBaseInfo.cpp 26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
30 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
91 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
93 if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit])
95 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
RISCVBaseInfo.h 289 // not supported for the given TT and FeatureBits combination.
290 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
307 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCSubtargetInfo.h 91 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
111 const FeatureBitset& getFeatureBits() const { return FeatureBits; }
113 FeatureBits = FeatureBits_;
119 return FeatureBits[Feature];
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
RISCVDisassembler.cpp 64 const FeatureBitset &FeatureBits =
68 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMInstPrinter.cpp 867 const FeatureBitset &FeatureBits = STI.getFeatureBits();
868 if (FeatureBits[ARM::FeatureMClass]) {
874 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
884 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
1300 const FeatureBitset &featureBits =
1303 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1349 const FeatureBitset &featureBits =
1352 bool hasD32 = featureBits[ARM::FeatureD32];
1675 const FeatureBitset &featureBits =
1738 (featureBits[ARM::HasV8_1MMainlineOps] &&
1747 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
2333 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
RISCVAsmParser.cpp 206 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val();
207 copySTI().setFeatureBits(FeatureBits);
208 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 450 // Selects a new architecture by updating the FeatureBits with the necessary
474 FeatureBitset FeatureBits = STI.getFeatureBits();
475 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
476 STI.setFeatureBits(FeatureBits);
8240 // Synchronize the abiflags information with the FeatureBits information we
8263 // Synchronize the abiflags information with the FeatureBits information we
8284 // Synchronize the ABI Flags information with the FeatureBits information we
8303 // Synchronize the ABI Flags information with the FeatureBits information we
8322 // Synchronize the ABI Flags information with the FeatureBits information we
8341 // Synchronize the ABI Flags information with the FeatureBits information w
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 5167 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits();
5168 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits))

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